Exploring Task Mappings on Heterogeneous MPSoCs using a Bias-Elitist Genetic Algorithm

Exploration of task mappings plays a crucial role in achieving high performance in heterogeneous multi-processor system-on-chip (MPSoC) platforms. The problem of optimally mapping a set of tasks onto a set of given heterogeneous processors for maximal throughput has been known, in general, to be NP-complete. The problem is further exacerbated when multiple applications (i.e., bigger task sets) and the communication between tasks are also considered. Previous research has shown that Genetic Algorithms (GA) typically are a good choice to solve this problem when the solution space is relatively small. However, when the size of the problem space increases, classic genetic algorithms still suffer from the problem of long evolution times. To address this problem, this paper proposes a novel bias-elitist genetic algorithm that is guided by domain-specific heuristics to speed up the evolution process. Experimental results reveal that our proposed algorithm is able to handle large scale task mapping problems and produces high-quality mapping solutions in only a short time period.Comment: 9 pages, 11 figures, uses algorithm2e.st

Modelling Performance Loss due to Thread Imbalance in Stochastic Variable-Length SIMT Workloads

When designing algorithms for single-instruction multiple-thread (SIMT) devices such as general purpose graphics processing units (GPGPUs), thread imbalance is an important performance consideration. Thread imbalance can emerge in iterative applications where workloads are of variable length, because threads processing larger amounts of work will cause threads with less work to idle. This form of thread imbalance influences the design space of algorithms-particularly in terms of processing granularity-but we lack models to quantify its impact on application performance. In this paper, we present a statistical model for quantifying the performance loss due to thread imbalance for iterative SIMT applications with stochastic, variable-length workloads. Our model is designed to operate with minimal knowledge of the implementation details of the algorithm, relying solely on an understanding of the probability distribution of the lengths of the workloads. We validate our model against a synthetic benchmark based on a Monte Carlo simulation of matrix exponentiation, and show that our model achieves nearly perfect accuracy. Compared to empirical data extracted from real hardware, our model maintains a high degree of accuracy, predicting mean performance loss within a margin of 2%.</p

Systematically Exploring High-Performance Representations of Vector Fields Through Compile-Time Composition

We present a novel benchmark suite for implementations of vector fields in high-performance computing environments to aid developers in quantifying and ranking their performance. We decompose the design space of such benchmarks into access patterns and storage backends, the latter of which can be further decomposed into components with different functional and non-functional properties. Through compile-time meta-programming, we generate a large number of benchmarks with minimal effort and ensure the extensibility of our suite. Our empirical analysis, based on real-world applications in high-energy physics, demonstrates the feasibility of our approach on CPU and GPU platforms, and highlights that our suite is able to evaluate performance-critical design choices. Finally, we propose that our work towards composing vector fields from elementary components is not only useful for the purposes of benchmarking, but that it naturally gives rise to a novel library for implementing such fields in domain applications.</p

Using Evolutionary Algorithms to Find Cache-Friendly Generalized Morton Layouts for Arrays

The layout of multi-dimensional data can have a significant impact on the efficacy of hardware caches and, by extension, the performance of applications. Common multi-dimensional layouts include the canonical row-major and column-major layouts as well as the Morton curve layout. In this paper, we describe how the Morton layout can be generalized to a very large family of multi-dimensional data layouts with widely varying performance characteristics. We posit that this design space can be efficiently explored using a combinatorial evolutionary methodology based on genetic algorithms. To this end, we propose a chromosomal representation for such layouts as well as a methodology for estimating the fitness of array layouts using cache simulation. We show that our fitness function correlates to kernel running time in real hardware, and that our evolutionary strategy allows us to find candidates with favorable simulated cache properties in four out of the eight real-world applications under consideration in a small number of generations. Finally, we demonstrate that the array layouts found using our evolutionary method perform well not only in simulated environments but that they can effect significant performance gains -- up to a factor ten in extreme cases -- in real hardware

Finding Morton-Like Layouts for Multi-Dimensional Arrays Using Evolutionary Algorithms

The layout of multi-dimensional data can have a significant impact on the efficacy of hardware caches and, by extension, the performance of applications. Common multi-dimensional layouts include the canonical row-major and column-major layouts as well as the Morton curve layout. In this paper, we describe how the Morton layout can be generalized to a very large family of multi-dimensional data layouts with widely varying performance characteristics. We posit that this design space can be efficiently explored using a combinatorial evolutionary methodology based on genetic algorithms. To this end, we propose a chromosomal representation for such layouts as well as a methodology for estimating the fitness of array layouts using cache simulation. We show that our fitness function correlates to kernel running time in real hardware, and that our evolutionary strategy allows us to find candidates with favorable simulated cache properties in four out of the eight real-world applications under consideration in a small number of generations. Finally, we demonstrate that the array layouts found using our evolutionary method perform well not only in simulated environments but that they can effect significant performance gains -- up to a factor ten in extreme cases -- in real hardware

Amnistía tributaria y el nivel de la recaudación del impuesto predial en la Municipalidad Distrital de Echarati, 2022

La investigación efectuada, tuvo por objetivo el determinar la relación entre la amnistía tributaria y el nivel de recaudación del Impuesto Predial en la Municipalidad Distrital de Echarati, 2022. El estudio desarrollado fue de tipo básica, considerando un diseño no experimental, transversal y correlacional; asimismo la muestra censal estuvo compuesta por 52 trabajadores de la Dirección de Administración y Finanzas de la Municipalidad Distrital de Echarati, empleando como técnica la encuesta y como medio de recolección el cuestionario compuesto por 19 ítems. Respecto a los resultados, se determinó que, el 69.23% de los trabajadores del Municipio Distrital de Echarati, refieren que la amnistía tributaria está en un proceso medio frente a la recaudación del impuesto predial, además el valor de p = 0.029 < 0.05 y una correlación de Spearman de 0.303 por lo que se aceptó la hipótesis del estudio. Se concluye que existe una relación entre la amnistía tributaria y la recaudación del impuesto predial en el Municipio Distrital de Echarati, con una correlación directa baja, por lo cual en la medida necesaria en que se aplique la amnistía tributaria se mejorará en forma regular la recaudación de impuesto predial

Combining on-hardware prototyping and high level simulation for DSE of multi-ASIP system

Abstract-Modern heterogeneous multi-processor embedded systems very often expose to the designer a large number of degrees of freedom, related to the application partitioning/mapping and to the component-and system-level architecture composition. The number is even larger when the designer targets systems based on configurable Application Specific Instructionset Processors, due to the fine customizability of their internal architecture. This poses the need for effective and user-friendly design tools, capable to deal with the extremely wide systemlevel design space exposed by multi-processor architecture and, at the same time, with an extended variety of processing element architectural configurations, to be evaluated in detail and in reasonable times. As a possible solution, within the MADNESS project [1], an integrated toolset has been proposed, combining the benefits of novel fast FPGA-based prototyping techniques with those provided by high-level simulation. In the toolset, the resulting evaluation platform serves as an underlying layer for a Design Space search algorithm. The paper presents the individual tools included in the toolset and their interaction strategy. The approach is then evaluated with a design space exploration case study, taking as a target application a video compression kernel. The integrated toolset has been used to produce a Pareto front of evaluated system-level configurations

Physical and functional interaction between A20 and ATG16L1-WD40 domain in the control of intestinal homeostasis

Prevention of inflammatory bowel disease (IBD) relies on tight control of inflammatory, cell death and autophagic mechanisms, but how these pathways are integrated at the molecular level is still unclear. Here we show that the anti-inflammatory protein A20 and the critical autophagic mediator Atg16l1 physically interact and synergize to regulate the stability of the intestinal epithelial barrier. A proteomic screen using the WD40 domain of ATG16L1 (WDD) identified A20 as a WDD-interacting protein. Loss of A20 and Atg16l1 in mouse intestinal epithelium induces spontaneous IBD-like pathology, as characterized by severe inflammation and increased intestinal epithelial cell death in both small and large intestine. Mechanistically, absence of A20 promotes Atg16l1 accumulation, while elimination of Atg16l1 or expression of WDD-deficient Atg16l1 stabilizes A20. Collectively our data show that A20 and Atg16l1 cooperatively control intestinal homeostasis by acting at the intersection of inflammatory, autophagy and cell death pathways

KIMSA DRINKS

En el presente documento de investigación académica, se desarrolló varios procesos de validación para una idea de negocio online para los usuarios que desean consumir bebidas alcohólicas fuera de lo tradicional. Kimsa Drinks consiste en una plataforma web que ofrece tres tipos de cajas diferentes con insumos, para la preparación de cócteles de cada una de las regiones. Todas las cajas comercializadas por Kimsa Drinks serán mediante packs regionales: Pack costa, Pack selva y Pack sierra. Asimismo, cada uno de los packs contiene un QR el cual te dirige a un video instructivo sobre la preparación del cóctel elegido.    Por un lado, se realizará un estudio de mercado analizando el público objetivo, los competidores que están ubicados en el presente mercado, entrevistas y focus para detectar a los clientes potenciales, encuestas para orientarnos en el precio y el diseño de la página web. Por otro lado, se evaluó el proyecto final, se realizó el estudio financiero para evaluar la rentabilidad del proyecto con una proyección de tres años el cual nos ayudó a determinar la inversión, viabilidad y financiamiento. Por último, se determinó que el proyecto es rentable a largo plazo debido a un VAN positivo.  In this academic research document, several validation processes were developed for an online business idea for users who want to consume non-traditional alcoholic beverages. Kimsa Drinks consists of a web platform that offers three different types of boxes with supplies, for the preparation of cocktails from each region. All the boxes marketed by Kimsa Drinks will be through regional packs: Costa Pack, Jungle Pack and Sierra Pack. Likewise, each of the packs contains a QR which directs you to an instructional video on the preparation of the chosen cocktail. On one hand, a market study will be carried out analyzing the target audience, the competitors that are located in the current market, interviews and focus to detect potential customers, surveys to guide us in the price and the design of the web page. On the other hand, the final project was evaluated, the financial study was carried out to evaluate the profitability of the project with a projection of three years, which helped us determine the investment, feasibility and financing. Finally, it was determined that the project is profitable in the long term due to a positive NPV.Trabajo de investigació