Implementation of ARTiS, an Asymmetric Real-Time Extension of SMP Linux

ARTiS is a real-time extension of GNU/Linux dedicated to SMP systems (Symmetric Multi-Processors). ARTiS divides the CPUs of an SMP system into two sets: real-time CPUs and non real-time CPUs. Real-time CPUs execute preemptible code only, thus tasks running on these processors perform predictably. If a task wants to enter into a non-preemptible section of code on a real-time processor, ARTiS will automatically migrate this task to a non real-time processor. Furthermore, dedicated load-balancing strategies allow all the system's CPUs to be fully exploited. \par The purpose of this paper is to describe the basic API that has been specified to deploy real-time applications, and to present the current implementation of the ARTiS model, which was achieved through modifications of the 2.6 Linux kernel. The implementation is build around an automatic migration of tasks between real-time and non real-time processors and the use of a load-balancer. The basic function of those mechanisms is to move a task structure from one processor to another. A strong constraint of the implementation is the impossibility for the code running on an RT processor to share a lock or to wait after another processor

Implementation of ARTiS, an Asymmetric Real-Time Extension of SMP Linux

ARTiS is a real-time extension of GNU/Linux dedicated to SMP systems (Symmetric Multi-Processors). ARTiS divides the CPUs of an SMP system into two sets: real-time CPUs and non real-time CPUs. Real-time CPUs execute preemptible code only, thus tasks running on these processors perform predictably. If a task wants to enter into a non-preemptible section of code on a real-time processor, ARTiS will automatically migrate this task to a non real-time processor. Furthermore, dedicated load-balancing strategies allow all the system's CPUs to be fully exploited. \par The purpose of this paper is to describe the basic API that has been specified to deploy real-time applications, and to present the current implementation of the ARTiS model, which was achieved through modifications of the 2.6 Linux kernel. The implementation is build around an automatic migration of tasks between real-time and non real-time processors and the use of a load-balancer. The basic function of those mechanisms is to move a task structure from one processor to another. A strong constraint of the implementation is the impossibility for the code running on an RT processor to share a lock or to wait after another processor

ARTiS, an Asymmetric Real-Time Scheduler for Linux on Multi-Processor Architectures

The ARTiS system is a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems. It allows to mix High Performance Computing and real-time. ARTiS exploits the SMP architecture to guarantee the preemption of a processor when the system has to schedule a real-time task. The implementation is available as a modification of the Linux kernel, especially focusing (but not restricted to) IA-64 architecture. The basic idea of ARTiS is to assign a selected set of processors to real-time operations. A migration mechanism of non-preemptible tasks insures a latency level on these real-time processors. Furthermore, specific load-balancing strategies permit ARTiS to benefit from the full power of the SMP systems: the real-time reservation, while guaranteed, is not exclusive and does not imply a waste of resources. This document describes the theoretical approach of ARTiS as well as the details of the Linux implementation. Several kind of measurements are also presented in order to validate the results

A Comparison of TSV Etch Metrology Techniques

International audienceWe use three metrology techniques, vertical scanning interferometry (VSI), confocal chromatic microscopy (CCM), and time domain optical coherence tomography (TD-OCT), for depth measurement of through-silicon vias (TSVs) of various cross sections and depths. The merits of these techniques are discussed and compared. Introduction While sales of semiconductor equipment broke a new record this year, many metrology needs should be addressed to support the development and production of electronic chips based on "More than Moore" scaling. Among these scaling approaches, 3D integration based on TSVs offers superior integration density and reduces interconnect length/latency. Measurements are needed to evaluate the depth uniformity of etched TSVs. Indeed, upon metal filling, geometrical variations of TSVs can affect Cu nails coplanarity and can warp the wafer, resulting in a low stacking yield. Measuring the depth of TSVs is an increasingly challenging task as the diameter of many TSVs has now shrunk to only a few microns

Automated method for the determination of a new matrix metalloproteinase inhibitor in ovine plasma and serum by coupling of restricted access material for on-line sample clean-up to liquid chromatography

A fully automated liquid chromatographic method was developed for the determination of Ro 28-2653, a new synthetic inhibitor of matrix metalloproteinases (MMPs), in ovine serum and plasma. The method was based on the coupling of a pre-column packed with restricted access material, namely LiChrospher RP-8 ADS (alkyl diol silica), for sample clean-up to an analytical column containing octyl silica stationary phase. One hundred mul of biological sample, to which 2-propanol was automatically added, were injected onto the ADS pre-column, which was then washed with a washing liquid consisting of a mixture of 25 mM phosphate buffer (pH 7.0) and acetonitrile (90: 10; v/v) for 10 min. By rotation of the switching valve, the analyte was then eluted in the back-flush mode with the LC mobile phase composed of a mixture of acetonitrile and 25 mM phosphate buffer (pH 7.0) (57:43; v/v). The UV detection was performed at 395 nm. The main parameters likely to influence the sample preparation technique were investigated. The method was then validated over a concentration range from 17.5 to 1950 ng/mI, the first concentration level corresponding to the lower limit of quantitation. At this concentration level, the mean bias and the R.S.D. value for intermediate precision were -2.4% and 4.2%, respectively. (C) 2004 Elsevier B.V. All rights reserved

Gaspard2 UML profile documentation

This document describes the current UML profile of Gaspard2. This profile extends the UML semantics to allow the user to describe a SoC (System-on-Chip) in three steps: the application (behavior of the Soc), the hardware architecture, and the association of the application to the hardware architecture. The application is represented following a data flow model, but additional mechanisms permit the usage of control flow on those applications. In addition to those notions, the profile contains a package introducing factorization mechanisms to enable the compact description of massively parallel and repetitive systems

A Model Driven Design Framework for High Performance Embedded Systems

Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. High performance embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their functionalities. The design of high performance embedded systems mainly relies on the following challenging issues: first, how to deal with the parallelism in order to increase the performances; second, how to abstract their implementation details in order to manage their complexity; third, how to refine these abstract representations in order to produce efficient implementations. This paper presents the Gaspard design framework for high performance embedded systems as a solution to the above issues. Gaspard uses the repetitive Model of Computation (MoC), which offers a powerful expression of the parallelism available in both system functionality and architecture. Embedded systems are designed at a high abstraction level with the MARTE (Modeling and Analysis of Real-time and Embedded systems) standard profile, in which our repetitive MoC is described by the so-called Repetitive Structure Modeling (RSM) package. Based on the Model-Driven Engineering (MDE) paradigm, MARTE models are refined towards lower abstraction levels, which make possible the design space exploration. By combining all these capabilities, Gaspard allows the designers to automatically generate code for formal verification, simulation and hardware synthesis from high level specifications of high performance embedded systems. Its effectiveness is demonstrated with the design of an embedded system for a multimedia application

COVID-19 symptoms at hospital admission vary with age and sex: results from the ISARIC prospective multinational observational study

Background: The ISARIC prospective multinational observational study is the largest cohort of hospitalized patients with COVID-19. We present relationships of age, sex, and nationality to presenting symptoms. Methods: International, prospective observational study of 60 109 hospitalized symptomatic patients with laboratory-confirmed COVID-19 recruited from 43 countries between 30 January and 3 August 2020. Logistic regression was performed to evaluate relationships of age and sex to published COVID-19 case definitions and the most commonly reported symptoms. Results: ‘Typical’ symptoms of fever (69%), cough (68%) and shortness of breath (66%) were the most commonly reported. 92% of patients experienced at least one of these. Prevalence of typical symptoms was greatest in 30- to 60-year-olds (respectively 80, 79, 69%; at least one 95%). They were reported less frequently in children (≤ 18 years: 69, 48, 23; 85%), older adults (≥ 70 years: 61, 62, 65; 90%), and women (66, 66, 64; 90%; vs. men 71, 70, 67; 93%, each P < 0.001). The most common atypical presentations under 60 years of age were nausea and vomiting and abdominal pain, and over 60 years was confusion. Regression models showed significant differences in symptoms with sex, age and country. Interpretation: This international collaboration has allowed us to report reliable symptom data from the largest cohort of patients admitted to hospital with COVID-19. Adults over 60 and children admitted to hospital with COVID-19 are less likely to present with typical symptoms. Nausea and vomiting are common atypical presentations under 30 years. Confusion is a frequent atypical presentation of COVID-19 in adults over 60 years. Women are less likely to experience typical symptoms than men

Caracterisation de structures MIS par methodes electriques et par ellipsometrie spectroscopique : application au transistor a effet de champ sur InP

SIGLECNRS T Bordereau / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Ordonnancement de systèmes parallèles temps réel (de la modélisation à la mise en oeuvre par l'ingénierie dirigée par les modèles)

Les travaux de cette thèse s'inscrivent dans le cadre de l'ordonnancement de calculs à haute performance sur multiprocesseurs à mémoire partagée. Ces travaux recouvrent deux parties distinctes. Dans une première partie nous abordons le flot de conception de systèmes-sur-puce muIti-processeurs. Nous proposons la modélisation de ces systèmes en UML afm de compléter la sémantique propre au parallélisme, et de permettre le raffinement du modèle de SoC jusqu'à une spécification complète, en restant au plus haut niveau de conception. Par la suite nous présentons un nouveau niveau de simulation qui, en prenant en compte le particularisme du traitement intensif de données, abstrait le fonctionnement du SoC. En particulier, l'exécution et l'ordonnancement des tâches sont directement effectués sur la machine hôte. La simulation, implémentée en SystemC, permet de très rapidement évaluer les performances d'un placement de données et de tâches sur une architecture. La compilation du modèle de SoC vers la simulation est faite à l'aide d'une chaîne de transformations de modèles. Nous détaillons les avantages apportés par l'usage de l'ingénierie dirigée par les modèles pour la conception de SoC. Enfin nous illustrons la mise en œuvre de l'ensemble du flot de conception développé au cours de la thèse avec un exemple d'exploration d'architecture.Dans une seconde partie, nous proposons une approche permettant d'exploiter les systèmes muIti-processeurs pour garantir les propriétés temps-réel d'applications parallèles. L'approche se base sur le fait que les tâches qui composent le système ont des priorités différentes, en particulier vis-à-vis du temps de réponse aux interruptions. L'introduction d'asymétrie parmi la liste d'ordonnancement des processeurs permet d'assurer de faibles latences pour les tâches à priorité temps-réel. Un équilibrage de charge adapté permet de maintenir toute la puissance potentielle des processeurs. Cette contribution est complétée d'une validation expérimentale basée sur une implémentation dans le noyau Linux.LILLE1-BU (590092102) / SudocSudocFranceF