Laser annealing of silicon on sapphire

Silicon-implanted silicon-on-sapphire wafers have been annealed by 50-ns pulses from a Q-switched Nd : YAG laser. The samples have been analyzed by channeling and by omega-scan x-ray double diffraction. After irradiation with pulses of a fluence of about 5 J cm^–2 the crystalline quality of the silicon layer is found to be better than in the as-grown state

Strain distributionand electronic property modifications in Si/Ge axial nanowires hetrostructures

Molecular dynamics simulations were carried out for Si/Ge axial nanowire heterostructures using modified effective atom method (MEAM) potentials. A Si–Ge MEAM interatomic cross potential was developed based on available experimental data and was used for these studies. The atomic distortions and strain distributions near the Si/Ge interfaces are predicted for nanowires with their axes oriented along the [111] direction. The cases of 10 and 25 nm diameter Si/Ge biwires and of 25 nm diameter Si/Ge/Si axial heterostructures with the Ge disk 1 nm thick were studied. Substantial distortions in the height of the atoms adjacent to the interface were found for the biwires but not for the Ge disks. Strains as high as 3.5% were found for the Ge disk and values of 2%–2.5% were found at the Si and Ge interfacial layers in the biwires. Deformation potential theory was used to estimate the influence of the strains on the band gap, and reductions in band gap to as small as 40% of bulk values are predicted for the Ge disks. The localized regions of increased strain and resulting energy minima were also found within the Si/Ge biwire interfaces with the larger effects on the Ge side of the interface. The regions of strain maxima near and within the interfaces are anticipated to be useful for tailoring band gaps and producing quantum confinement of carriers. These results suggest that nanowire heterostructures provide greater design flexibility in band structure modification than is possible with planar layer growth

Impurity gettering

Transition metal impurities are well known to cause detrimental effects when present in the active regions of Si devices. Their presence degrades minority carrier lifetime, provides recombination-generation centers, increases junction leakage current and reduces gate oxide integrity. Thus, gettering processes are used to reduce the available metal impurities from the active region of microelectronic circuits. Gettering processes are usually divided into intrinsic (or internal) and extrinsic (or external) categories. Intrinsic refers to processing the Si wafer in a way to make available internal gettering sites, whereas extrinsic implies externally introduced gettering sites. Special concerns have been raised for intrinsic gettering. Not only will the formation of the precipitated oxide and denuded zone be difficult to achieve with the lower thermal budgets, but another inherent limit may set in. In this or any process which relies on the precipitation of metal silicides the impurity concentration can only be reduced as low as the solid solubility limit. However, the solubilities of transition metals relative to silicide formation are typically found to be {approx_gt}10{sup 12}/cm{sup 3} at temperatures of 800 C and above, and thus inadequate to getter to the needed concentration levels. It is thus anticipated that future microelectronic device processing will require one or more of the following advances in gettering technology: (1) new and more effective gettering mechanisms; (2) quantitative models of gettering to allow process optimization at low process thermal budgets and metal impurity concentrations, and/or (3) development of front side gettering methods to allow for more efficient gettering close to device regions. These trend-driven needs provide a driving force for qualitatively new approaches to gettering and provide possible new opportunities for the use of ion implantation in microelectronics processing

Ion channeling studies of hydrogen lattice location

The application of ion channeling to study the lattice site location of hydrogen in solids is briefly reviewed. The technique has been applied to both metals and semiconductors and is particularly valuable when combined with ion implantation for the introduction of hydrogen in the study of hydrogen trapping by defects

Channeling in Semiconductors and its Application to the Study of Ion Implantation

The channeling characteristics of protons and helium ions in various diamond-type lattices (diamond, Si, Ge, GaP, GaAs, GaSb) have been studied by means of elastic backscattering in the 0.5 to 2 MeV range. Critical angles (ψ½) and minimum yields (ψ½) have been measured and compared to theory. The values of ψ½ for axial channeling have a functional dependence which agrees well with calculations based on the average potential along the row - both for uniform and for non-uniform spacing and (in the case of the compound semiconductors) for mixed atomic composition. Planar critical angles also show a functional dependence in agreement with average potential calculations. However, it is necessary to include in the calculation the effect of surface transmission which becomes increasingly important for higher order planar directions (e.g. lower atomic density of the planes). Measured full angular distributions are compared with calculated distributions for planar channeling. For both axial and planar channeling the measured critical angles are ≈ 25% lower in absolute magnitude than calculated. Channeling and electrical measurements are combined to study ion implanted impurities in silicon. The lattice disorder and impurity atom lattice location are investigated by channeling effect measurements using a 1 MeV helium ion analyzing beam. The electrical type, number of carriers/cm2 and mobility are determined by use of Hall effect and sheet resistivity measurements. The anneal behavior of Cd and Te implantations (20-50 keV) into Si at substrate temperatures of 23°C and 350°C were investigated. The room temperature Te implants showed substitutional behavior and donor action after anneal at 600°C. In room temperature Cd implantations, outdiffusion of the Cd was observed when the disordered layer annealed. Implantations of Cd at 350°C indicated the presence of an interstitial component and n-type behavior was observed.</p

Release of H and He from TiC, stainless steel and graphite by pulsed electron and furnace heating

The release of implanted D and /sup 3/He from TiC coatings, SS 304 and graphite by pulsed electron beam (e-beam) heating and furnace heating has been investigated. Low fluence implants of D or /sup 3/He and saturation fluence D implants have been studied for 0.5 - 1.5 keV D and 3 keV /sup 3/He. The retained D or /sup 3/He was monitored by ion beam analysis. The 50 ns e-beam pulsing resulted in the release of D in all materials and was compared with release during isochronal annealing in a furnace. A substantial enhancement in the fractional D release was found for D saturated TiC (0.25 D to host atom ratio) compared with low fluence implants. In contrast no enhancement of D release was observed for D saturated graphite and SS 304 compared with low fluence implants. Release of /sup 3/He from TiC was also obtained by e-beam pulsed heating and this release was not affected by the presence of saturation concentrations of D. Comparison to furnace anneals and the calculated time evolution of the temperature profiles suggests a simple model for the D release based on diffusion-limited release in the case of pulsed e-beam treatments and trap-limited release in the case of furnace bulk heating. These processes are closely related to hydrogen recycle in tokamaks and have implications for T inventory control and He ash removal

Depth profiles of perpendicular and parallel strain in a GaAsxP1−x/GaP superlattice

Using double-crystal x-ray rocking curves, depth profiles of parallel and perpendicular strain were obtained in a GaAs0.14P0.86/GaP superlattice grown on a buffer layer on (100) GaP. Combining symmetric Fe Kα1 (400) and asymmetric Cu Kα1 (422) reflections, a constant parallel strain of 0.19% relative to the substrate was found throughout the superlattice and buffer layer. Relative to the substrate, the perpendicular strain was found to be 0.26% in the buffer, and 0.80% and −0.19% in the 176-Å-thick superlattice GaAsxP1−x and GaP layers, respectively. The strain profiles indicate the buffer is ~80% decoupled from the substrate by misfit dislocations near the buffer/substrate interface, and the lattice misfit in the superlattice is elastically accommodated by the epitaxial structure with a small shift in the average lattice constant relative to the equilibrium superlattice structure