Tetrix depressa (Brisout, 1848) une espèce d’orthoptère nouvelle pour la Vendée (Orthoptera, Tetrigidae)

The writer describes the discovery of Depressed Groundhopper, Tetrix depressa (Brisout, 1848) in a disused quarry in Benet. It's a new species of Groundhopper in Vendée (France)

Approches légères pour le raisonnement sur les connaissances et les croyances

Dans cette thèse nous étudions un cadre simple dans lequel modéliser les croyances et les connaissances ainsi que leur évolution dans des systèmes multi-agents. La logique standard de représentation des connaissances est très expressive, mais au prix d'une haute complexité calculatoire. Nous proposons ici un cadre qui permet de capturer plus de situations que d'autres approches existantes tout en restant efficace. En particulier, nous considérons l'application de notre logique à la planification épistémique : étant données une situation initiale et des actions possibles, peut-on atteindre un but fixé ? Cela peut signifier savoir à qui poser des questions pour apprendre des informations, faire en sorte de ne pas être remarquée lorsque l'on lit le courrier de quelqu'un d'autre, ou empêcher quelqu'un d'entendre nos secrets. Nous considérons aussi de possibles extensions à des logiques de croyance, ainsi que les liens entre notre système et d'autres cadres proches.In this thesis we study a lightweight framework in which to model knowledge and beliefs and the evolution thereof in multiagent systems. The standard logic used for this is very expressive, but this comes at a high cost in terms of computational efficiency. We here propose a framework which captures more than other existing approaches while remaining cost-effective. In particular, we show its applicability to epistemic planning: given an initial situation and some possible actions, can we find a way to reach our desired goal? This might mean knowing who to ask in order to learn something, making sure we aren't seen when reading someone else's mail, or preventing someone from overhearing our secrets. We also discuss possible extensions to logics of belief, and the relations between our framework and other related approaches

The TASTE Toolset: turning human designed heterogeneous systems into computer built homogeneous software.

The TASTE tool-set results from spin-off studies of the ASSERT project, which started in 2004 with the objective to propose innovative and pragmatic solutions to develop real-time software. One of the primary targets was satellite flight software, but it appeared quickly that their characteristics were shared among various embedded systems. The solutions that we developed now comprise a process and several tools ; the development process is based on the idea that real-time, embedded systems are heterogeneous by nature and that a unique UML-like language was not helping neither their construction, nor their validation. Rather than inventing yet another "ultimate" language, TASTE makes the link between existing and mature technologies such as Simulink, SDL, ASN.1, C, Ada, and generates complete, homogeneous software-based systems that one can straightforwardly download and execute on a physical target. Our current prototype is moving toward a marketed product, and sequel studies are already in place to support, among others, FPGA systems

Premier inventaire des Orthoptères de l’île d’Yeu (Vendée)

A first inventory of Yeu island’s Orthoptera (Vendée, France) allow us to list 23 species and 4 species of the allied orders Mantodea, Phasmodea and Dermaptera. A faunistic study was established on each species and a discussion gives an evaluation of the imprint of human activity on insular Orthoptera’s communities

Turning block-sequential automata networks into smaller parallel networks with isomorphic limit dynamics

We state an algorithm that, given an automata network and a block-sequential update schedule, produces an automata network of the same size or smaller with the same limit dynamics under the parallel update schedule. Then, we focus on the family of automata cycles which share a unique path of automata, called tangential cycles, and show that a restriction of our algorithm allows to reduce any instance of these networks under a block-sequential update schedule into a smaller parallel network of the family and to characterize the number of reductions operated while conserving their limit dynamics. We also show that any tangential cycles reduced by our main algorithm are transformed into a network whose size is that of the largest cycle of the initial network. We end by showing that the restricted algorithm allows the direct characterization of block-sequential double cycles as parallel ones.Comment: Accepted at CIE 202

GFM-Voc: A real-time voice quality modification system

International audienc

Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system allows to improve its efficiency and its flexibility thanks to their programmability. To exploit these devices, the designer has to identify the functionalities that have to be executed on them and provide their implementation by means of Hardware Description Languages. Generating these descriptions for a software developer could be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). State of the art tools implementing such methodologies have not been designed for the integration with aerospace systems design flows, so significant adaptations could be required to the designer for integrating the hardware implementations with the rest of the design solution. In this paper the integration of a High Level Synthesis design flow in the TASTE framework (http://taste.tuxfamily.org) is presented. TASTE is a set of freely available tools for the development of real time embedded systems developed by the European Space Agency together with a set of its industrial partners. This framework allows to integrate specifications described in different languages (e.g., C, ADA, Simulink, SDL) by means of formal languages (AADL and ASN.1) and to early verify the correctness of the produced solutions. TASTE has been extended with Bambu (http://panda.dei.polimi.it), a tool for the High Level Synthesis developed at Politecnico di Milano. In this way the TASTE users have the possibility to specify which functionalities, provided by means of high level languages such C, have to be implemented in hardware on the FPGA without having to directly provide the hardware implementations. Thanks to the integration of the High Level Synthesis tool indeed, the framework is able not only to produce the hardware implementations, but also to integrate them in the rest of the aerospace system by automatically generating the whole architecture to be implemented on the FPGA. This architecture contains not only the implementation of the hardware accelerators, but also of the components required to transfer the data from and to the rest of the system and to correctly manage their size and endianness. The application of the extended framework to a real case study shows its effective usability

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system improves its efficiency and its flexibility thanks to their programmability, but increases the design complexity. The design flows indeed have to be composed of several steps to fill the gap between the starting solution, which is usually a reference sequential implementation, and the final heterogeneous solution which includes custom hardware accelerators. Among these steps, there are the analysis of the application to identify the functionalities that gain advantages in execution on hardware and the generation of their implementations by means of Hardware Description Languages. Generating these descriptions for a software developer can be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). With respect to other embedded systems scenarios, the aerospace systems introduce further constraints that have to be taken into account during the design of these heterogeneous systems. In this type of systems explicit data transfers to and from FPGAs are preferred to the adoption of a shared memory architecture. The first approach indeed potentially improves the predictability of the produced solutions, but the sizes of all the data transferred to and from any devices must be known at design time. Identifying the sizes in presence of complex C applications which use pointers can be a not so easy task. In this paper, a semi-automatic design flow based on the integration of an aerospace design flow, an application analysis technique, and High Level Synthesis methodologies is presented. The initial reference application is analyzed to identify which are the sizes of the data exchanged among the different components of the application. Next, starting from the high level specification and from the results of this analysis, High Level Synthesis techniques are applied to automatically produce the hardware accelerators