Bipolar effects in unipolar junctionless transistors

In this work, we analyze hysteresis and bipolar effects in unipolar junctionless transistors. A change in subthreshold drain current by 5 orders of magnitude is demonstrated at a drain voltage of 2.25 V in silicon junctionless transistor. Contrary to the conventional theory, increasing gate oxide thickness results in (i) a reduction of subthreshold slope (S-slope) and (ii) an increase in drain current, due to bipolar effects. The high sensitivity to film thickness in junctionless devices will be most crucial factor in achieving steep transition from ON to OFF state. (C) 2012 American Institute of Physics. (http://dx.doi.org/10.1063/1.4748909

Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells

Thin-oxide Z2-FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FD SOI technology. Nevertheless a performance drop and higher variability with respect to thicker oxide Z2-FET cells are observed.H2020 REMINDER European project (grant agreementNo 687931) and TEC2014-59730 are thanked for financialsupport

Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM

This article has been accepted for publication by IEEE "Navarro Moral, C.; et al. Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM. IEEE Transactions on Electron Devices, 64(11): 4486-4491 (2017). DOI: 10.1109/TED.2017.2751141(c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works."The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions

A virtual SOI diode with electrostatic doping

session 5: Nanoscale DevicesInternational audienceHighly reconfigurable FD-SOI diodes with electrostatic doping controlled by gate bias are presented experimentally for the first time. Measurements show that the virtual p-n junction with gate-induced free carriers exhibits diode-like characteristics. A clear advantage of the virtual diode is that the doping levels are adjustable by the front and back gate biases. This flexibility enables the tuning of reverse current, forward current and breakdown voltage. Measurements and simulations explain why the models developed for standard diodes with physical doping do not apply

Back-gate effects and mobility characterization in junctionless transistor

International audienceThis work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation

Back-gate effects and detailed characterization of junctionless transistor

session C4L-E: Characterization of Advanced DevicesInternational audienceThe work addresses effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced FDSOI technology. A systematic methodology to extract and discriminate the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the properties of back channel in ultra-thin heavily doped JL devices. It has been demonstrated that both volume and accumulation-mode mobilities increase when the front surface is in accumulation

Modelling of Z2-FET memory cell

International audienc

MSDRAM, A2RAM and Z 2 -FET performance benchmark for 1T-DRAM applications

session Memory (12.4)International audienceIn this study, we propose a benchmark of performance between three promising 1T-DRAM device structures on SOI substrate: MSDRAM, A2RAM and Z 2 -FET. For a fair comparison, TCAD simulation with the same basic calibration and typical 28FDSOI technological parameters was used. The merits and limitations of each variant are discussed

A comprehensive model on field-effect pnpn devices (Z 2 -FET)

International audienceA comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived