Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a 28 Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick 28 Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz ½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to -gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system. Charge noise degrades the performance of spin qubits hindering scalability. Here the authors engineer the heterogeneous material stack in 28 Si/SiGe gate-defined quantum dots, to improve the scattering properties and to reduce charge noise

Author Correction : Reducing charge noise in quantum dots by using thin silicon quantum wells

The original version of this Article omitted fromthe author list the author Amir Sammakwho is from the 'QuTech and Netherlands Organisation for Applied Scientific Research (TNO), Delft, The Netherlands'. This has been corrected in both the PDF and HTML versions of the Article

CMOS-based cryogenic control of silicon quantum circuits

The most promising quantum algorithms require quantum processors hosting millions of quantum bits when targeting practical applications. A major challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, a major bottleneck appears between the quantum chip in a dilution refrigerator and the room temperature electronics. Advanced lithography supports the fabrication of both CMOS control electronics and qubits in silicon. When the electronics are designed to operate at cryogenic temperatures, it can ultimately be integrated with the qubits on the same die or package, overcoming the wiring bottleneck. Here we report a cryogenic CMOS control chip operating at 3K, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20mK. We first benchmark the control chip and find electrical performance consistent with 99.99% fidelity qubit operations, assuming ideal qubits. Next, we use it to coherently control actual silicon spin qubits and find that the cryogenic control chip achieves the same fidelity as commercial instruments. Furthermore, we highlight the extensive capabilities of the control chip by programming a number of benchmarking protocols as well as the Deutsch-Josza algorithm on a two-qubit quantum processor. These results open up the path towards a fully integrated, scalable silicon-based quantum computer

Supplemental data for the paper: Multiplexed quantum transport using commercial off-the-shelf CMOS at sub-kelvin temperatures

Original dataset underlying the article "Multiplexed quantum transport using commercial off-the-shelf CMOS at sub-kelvin temperatures", to reproduce figures 3,4,5. [ Correspondence to: [email protected]

Data to generate the figures in the article: Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots

   The datasets contains the data necessary to generate figures in the article  https://arxiv.org/abs/2112.09606, to be published in Nature Communication. We report both text files containing the data  and the script file (python or matlab) that is used to generate figure panels from the data file in the same folder. Specifically, we include experimental data for electrical characterisation of valley splitting in quantum dots from two-dimensional electron gases in Si/SiGe heterostructures and theory simulations.” </p

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise degrades the performance of spin qubits hindering scalability. Here the authors engineer the heterogeneous material stack in 28Si/SiGe gate-defined quantum dots, to improve the scattering properties and to reduce charge noise

Shallow and Undoped Germanium Quantum Wells: A Playground for Spin and Hybrid Quantum Technology

Buried-channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 105 cm2 V−1 s−1) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top-gate of a dopant-less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 1011cm−2, light effective mass (0.09me), and high effective g-factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies.Business DevelopmentQuTechQCD/Scappucci LabQCD/Veldhorst La

Shallow and Undoped Germanium Quantum Wells: A Playground for Spin and Hybrid Quantum Technology

Buried-channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 10 5 cm 2 V −1 s −1 ) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top-gate of a dopant-less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 10 11 cm −2 , light effective mass (0.09m e ), and high effective g-factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies. © 2019 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinhei