Multi-bit sigma-delta modulators with enhanced dynamic-range using non-linear DAC for hearing aids

15th IEEE International Conference on Electronics, Circuits and Systems, MaltaThis paper presents the possibility of employing nonlinear low-resolution DACs in the feedback paths of multi-bit second-order Sigma-Delta modulators. The proposed technique is particularly attractive in applications such as hearing aids, requiring a very large dynamic range and medium signal-tonoise-plus-distortion-ratio. As demonstrated through simulated results in which noise and mismatch effects are included, for the same over-sampling ratio, improvements in the order of 6-to-9 dB in the dynamic range can be achieved when comparing with the same topology employing linear-DACs

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUAA low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme

Digital-domain self-calibration technique for video-rate pipeline A/D converters using Gaussian white noise

Electronics Letters Vol.38, nº 19A digital-domain selfsalibmtion technique for video-rate pipeline AID converters based an a Gaussian white noise input signal is presented. The pmposed algorithm is simple and efficient. A design example is shown 10 illustrate that the overall linemiry of a pipeline ADC can be highly improved using this technique

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths

Controlo por fase única de conversores A/D de baixa tensão

Este trabalho apresenta a aplicação de um controlo de fase única a um conversor concorrencial de baixa tensão. Com vista à validação da análise e conclusão teóricas, um conversor concorrencial de 10-bit 4 MS/s foi projectado e simulado. Foi primeiramente simulado com um controlo clássico de 6 fases, e posteriormente com um esquema de fase única. Os resultados de simulação mostram que as características globais são mantidas, apontando para que o uso de esquemas de fase única em conversores de baixa tensão seja uma solução que reduz a complexidade dos sistemas clássicos não sobrepostos.info:eu-repo/semantics/publishedVersio

Physical Function and Quality of Life After Resection of Mobile Spine Chondrosarcoma.

Study Design:Retrospective cohort study. Objectives:(1) To assess patient-reported outcomes-physical function, pain, and quality of life-in patients who underwent resection of a mobile spine chondrosarcoma. (2) To assess complications (90 days), readmissions, reoperations, oncological outcomes, and neurologic status. Methods:Thirty-three patients with spinal conventional chondrosarcoma resection between 1984 and 2014 at one hospital were included. The primary outcome measures were-minimally 6 months after surgery-the EuroQol 5 Dimensions (EQ5D), PROMIS-Physical Function, PROMIS-Pain Intensity, and Oswestry (ODI) Disability Index, or Neck (NDI) Disability established in 14 out of 20 alive (70.0%) patients. Complications, readmission, reoperations, oncological outcomes, and neurological status were reported for the complete cohort of 33 patients. Results:After spine chondrosarcoma resection, patients (n = 14) reported worse physical function (median 43, range 22-61, P = .026), worse quality of life (median EQ5D 0.70, range 0.04-1, P = .022), and comparable pain intensity (median 47, range 31-56, P = .362) when compared with US general population values. The median NDI/ODI was 25 (range 0-72) indicating mild to moderate disability. Patients undergoing reoperation had worse patient-reported outcomes than those who did not. Eighteen (55.5%) out of 33 patients suffered complications (90 days), 14 (42.4%) had unplanned readmission, and 13 (39.4%) underwent reoperation. Intralesional resection was associated with increased readmission, reoperation, and recurrence rate. Conclusions:Chondrosarcoma affects quality of life and physical function and its treatment frequently results in complications and reoperations. Our findings can be used to inform future patients about expected outcomes

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

15th IEEE International Conference on Electronics, Circuits and Systems, MaltaIn this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, PolóniaIn this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are required but, instead, simple sourcefollowers are used to provide the required isolation. Simulation results show that linearity levels better than 60dB and gain accuracies of better than 1.6% are achieved making this circuit well suited to be used in ultra low-power highspeed 6-to-8 bits pipeline or multi-stage algorithmic ADCs

New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise

IEEE International Symposium on Circuits and Systems, pp. 232 – 235, Seattle, EUAThis paper describes a new digital-domain selfcalibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This lowamplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then used to calculate the required calibrating-codes. As an example, the calibration of a 13-bit pipeline ADC shows that the overall linearity can be significantly improved using this technique