A new approach for minimizing buffer capacities with throughput constraint for embedded system design

International audienceThe design of streaming applications (e.g. multimedia or network packet processing) must consider several optimizations such as the minimization of the whole surface of the memory needed on a Chip. The problem tackled in this paper is the minimization of the whole surface of the memory needed to reach a minimum fixed throughput. The application is modelled using a Marked Timed Weighted Event Graphs (in short MTWEG), which is a subclass of Petri nets. Transitions correspond to specific treatments and places model buffers for data transfers. It is assumed that transitions are periodically fired with a fixed throughput. The problem is first mathematically modelled using an Integer Linear Program. We then study for a unique buffer the optimum throughput according to its capacity. A polynomial simple algorithm that minimizes the overall surface of memory for a fixed throughput is derived when there is no circuit in the initial MTWEG, which corresponds to a wide class of applications. We prove in this case that the capacities of every buffer may be optimized independently. For general MTWEG, the problem is NP-Hard and an original polynomial 2-approximation algorithm is presented. For practical applications, the solution computed is very close to the optimum

A polynomial algorithm for the computation of buffer capacities with throughput constraint for embedded system design

International audienceMarked timed weighted event graphs (in short MTWEG), which are a subclass of Petri nets, are widely used for modelling practical industrial problems. In this paper, a central practical problem for the design of streaming (e.g. multimedia or network packet processing) is modelled using a MTWEG. The optimization problem tackled here consists then on finding an initial marking minimizing the overall number of tokens for a minimum given throughput. If the firings of the transitions are periodic, this problem is NP-complete and can be modelled using an integer linear program. A general lower bound on the minimum overall capacity is then proved. If the initial MTWEG has a unique circuit, a polynomial time algorithm based on the resolution of a particular Diophantine equation is presented to solve it exactly. We lastly experiment it on an industrial example

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

International audienceThe growing requirement on the correct design of a high performance DSP system in short time force us to use IP's in many design. In this paper, we propose an efficient IP block based design environment for high throughput VLSI systems. The flow generates SystemC register transfer level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement process inserts automatically control structures to treat delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The experimentations show that the approach can produce efficient RTL architecture and allow a huge save of time

Matlab based environment for designing DSP systems using IP blocks

International audienceIn this paper, we propose an efficient IP block based design environment for high throughput VLSI Systems. The flow generates SystemC Register Transfer Level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. This experimentations show that the approach can produce efficient RTL architecture and allow for huge saving of time

An efficient methodology and semi automated flow for design and validation of complex digital signal processing ASICS macro cells

We present a methodology and design flow for signal processing application specific integrated circuit macro-cells. The key features of the methodology are the mastering the complexity of design, the increasing of reuse factor and the early error detection. It takes advantages of a derivative designs, a signal processing modularity, generic modeling and combines both levels of abstraction, in order to produce an efficient architecture. The flow includes a fast verification platform that drives both algorithm and architecture validation in an efficient way. We illustrate the effectiveness of the proposed methodology by a significant industrial application. Experimental design results indicate strong advantages of the proposed schemes

Utilisation d'une méthode de correction de retards pour la vérification d'un assemblage de fonctions RTL par rapport à un assemblage de fonctions au niveau fonctionnel

National audienceLe processus de conception est actuellement bien maîtrisé du modèle RTL jusquau silicium pour lesapplications de traitement du signal. Les applications de traitement du signal deviennent de plus en pluscomplexes. Une façon de maîtriser cette complexité grandissante est délever le niveau dabstraction jusquauniveau fonctionnel. Ces applications sont généralement composées de sous-fonctions typiques et bien connuespouvant être validées indépendamment. Deux modèles de chaque sous-fonction peuvent alors être réalisés etvalidés au niveau fonctionnel et au niveau RTL. Lapplication complète de traitement du signal est modélisée auniveau fonctionnel et au niveau RTL en assemblant de la même façon plusieurs sous-fonctions pré-conçues. Bienquindividuellement les modèles RTL et fonctionnel des sous-fonctions produisent les mêmes sorties à un retardprès, le passage de lassemblage de ces sous-fonctions au niveau fonctionnel à lassemblage au niveau RTLentraîne une différence de comportement de lapplication complète : les sorties de lapplication complète auniveau fonctionnel et au niveau RTL ne sont plus identiques numériquement. Ce problème complique alors lavérification entre les deux niveaux dabstraction. Dans ce papier, nous analysons les causes de cette différence.Nous proposons une méthode systématique de correction (appelée correction de retards). Cette méthode estappliquée sur une chaîne de modulation numérique

A Design Flow Dedicated to Multi-mode Architectures for DSP Applications

International audienceThis paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single RTL hardware architecture optimized in area is generated. In order to reduce the register, steering logic (multiplexers) and controller (decoding logic) complexities, we propose a joint-scheduling algorithm which maximizes the similarities between control steps and specific binding approaches for both functional units and storage elements which maximize the similarities between the datapaths. We show through a set of test cases that our approach offers significant area saving relative to the state-of-the-art

A 1.62GS/s Time-Interleaved SAR ADC with fully digital background mismatch calibration achieving interleaving spurs below 70dBFS

International audienceToday's applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed entirely in the digital domain through equalization