A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Design of RC-active oscillators using composite amplifiers

The design of composite opamp Wien-Bridge oscillators is systematically approached by using a general model including amplitude control issues. Two different design criteria are presented and their main features summarized. A general composite opamp topology from which a catalog of structures can be obtained in a systematic way is presented. Experimental data are included illustrating the performance of the proposed design criteria

Behavioral modeling of PWL analog circuits using symbolic analysis

Behavioral models are used both for top-down design and for bottom-up verification. During top-down design, models are created that reflect the nominal behavior of the different analog functions, as well as the constraints imposed by the parasitics. In this scenario, the availability of symbolic modeling expressions enable designers to get insight on the circuits, and reduces the computational cost of design space exploration. During bottom-up verification, models are created that capture the topological and constitutive equations of the underlying devices into behavioral descriptions. In this scenario symbolic analysis is useful because it enables to automatically obtain these descriptions in the form of equations. This paper includes an example to illustrate the use of symbolic analysis for top-down design.Comisión Interministerial de Ciencia y Tecnología TIC97-058

A new nonlinear time-domain op-amp macromodel using threshold functions and digitally controlled network elements

A general-purpose nonlinear macromodel for the time-domain simulation of integrated circuit operational amplifiers (op amps), either bipolar or MOS, is presented. Three main differences exist between the macromodel and those previously reported in the literature for the time domain. First, all the op-amp nonlinearities are simulated using threshold elements and digital components, thus making them well suited for a mixed electrical/logical simulator. Secondly, the macromodel exhibits a superior performance in those cases where the op amp is driven by a large signal. Finally, the macromodel is advantageous in terms of CPU time. Several examples are included illustrating all of these advantages. The main application of this macromodel is for the accurate simulation of the analog part of a combined analog/digital integrated circui

A 74dB Dynamic Range, 1.1-MHz Signal Band 4th-Order 2-1-1 Cascade Multi-Bit CMOS ΣΔ Modulator for ADSL

This paper explores the use of ΣΔ techniques for A/D conversion exceeding 1-MHz signal bandwidth. A cascade modulator architecture is proposed which combines single-bit and multi-bit quantization to obtain more than 12-b Dynamic Range (DR) with an oversampling ratio of only 16, and with neither calibration nor trimming required. Measurements from a 0.7mm CMOS prototype show 74dB DR in 1.1-MHz signal band at 35.7-MHz clock rate, with a power consumption of 55mW from a 5-V supply.This work has been supported by the European Union, under ESPRIT Project 8795-AMFIS.Peer reviewe

Chaos From Switched-Capacitor Circuits: Discrete Maps

A special-purpose analog computer made of switched-capacitor circuits is presented for analyzing chaos and bifurcation phenomena in nonlinear discrete dynamical systems modeled by discrete maps *n + t = fan)-Experimental results are given for four switched-capacitor circuits described by well-known discrete maps; namely, the logistic map, the piecewise-linear unimodal (one-hump) map, the H é non map, and the Lozi map

A Tool for automated design of sigma-delta modulators using statistical optimization

A tool is presented which starting from high level specifications of SC σδ modulators (resolution, bandwidth and oversampling ratio) calculates first optimum specifications for the building blocks (op-amps, comparator, etc.), and then, optimum sizes for their schematics. At both design levels (high-level synthesis and cell dimensioning), optimization is performed via using statistical techniques and innovative heuristics, which allow global design (independent on the initial conditions) and increased computer efficiency as compared to conventional statistical optimization techniques. The tool has been conceived to be flexible at the high-level part(via the use of an architecture independent, behaviourable modeling approach) and completely open at the cell-design part. Performance of the tool is demonstrated via the automatic design of a 16bit-dynamic range, 8Khz second-order SC σδ modulator in 1.2 μm CMOS technology, for which measurements on a fabricated prototype are reported

Modeling OpAmp-induced harmonic distortion for switched-capacitor ΣΔ modulator design

This communication reports a new modeling of opamp-induced harmonic distortion in SC ΣΔ modulators, which is aimed to optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer of charge in a SC integrator and use power expansion and nonlinear fitting to obtain analytical models to represent harmonic distortion as function of the opamp finite gain-bandwidth (GB), slew-rate (SR) and nonlinear DC gain. Calculated models apply for all modulator architectures where harmonic distortion is dominated by the first integrator in the chain. We show that results provided by the new analytical models fit well to that obtained by simulation in time domain and have accuracy levels much larger than that provided by previously reported modeling approaches

Chaos via a piecewise-linear switch ed-capacitor circuit

A nonlinear switched-capacitor circuit that generates chaotic signals is reported. The circuit is described by a first-order piecewise-linear discrete equation that exhibits a chaotic dynamics. Experimental results illustrating the circuit performance and its use as a noise generator are included.Comisión Interministerial de Ciencia y Tecnología 3467-8