Advances in ILP-based Modulo Scheduling for High-Level Synthesis

In today's heterogenous computing world, field-programmable gate arrays (FPGA) represent the energy-efficient alternative to generic processor cores and graphics accelerators. However, due to their radically different computing model, automatic design methods, such as high-level synthesis (HLS), are needed to harness their full power. HLS raises the abstraction level to behavioural descriptions of algorithms, thus freeing designers from dealing with tedious low-level concerns, and enabling a rapid exploration of different microarchitectures for the same input specification. In an HLS tool, scheduling is the most influential step for the performance of the generated accelerator. Specifically, modulo schedulers enable a pipelined execution, which is a key technique to speed up the computation by extracting more parallelism from the input description. In this thesis, we make a case for the use of integer linear programming (ILP) as a framework for modulo scheduling approaches. First, we argue that ILP-based modulo schedulers are practically usable in the HLS context. Secondly, we show that the ILP framework enables a novel approach for the automatic design of FPGA accelerators. We substantiate the first claim by proposing a new, flexible ILP formulation for the modulo scheduling problem, and evaluate it experimentally with a diverse set of realistic test instances. While solving an ILP may incur an exponential runtime in the worst case, we observe that simple countermeasures, such as setting a time limit, help to contain the practical impact of outlier instances. Furthermore, we present an algorithm to compress problems before the actual scheduling. An HLS-generated microarchitecture is comprised of operators, i.e. single-purpose functional units such as a floating-point multiplier. Usually, the allocation of operators is determined before scheduling, even though both problems are interdependent. To that end, we investigate an extension of the modulo scheduling problem that combines both concerns in a single model. Based on the extension, we present a novel multi-loop scheduling approach capable of finding the fastest microarchitecture that still fits on a given FPGA device - an optimisation problem that current commercial HLS tools cannot solve. This proves our second claim

Automatic measurement of departing times in smartphone alerting systems: A pilot study

Aim Smartphone alerting systems (SAS) alert volunteers in close vicinity of suspected out-of-hospital cardiac arrest. Some systems use sophisticated algorithms to select those who will probably arrive first. Precise estimation of departing times and travel times may help to further improve algorithms. We developed a global positioning system (GPS) based method for automatic measurements of departing times. The aim of this pilot study was to evaluate feasibility and precision of the method. Methods Region of Lifesavers alerting app (iOS/ Android, version 3.0, FirstAED ApS, Denmark) was used in this study. 27 experiments were performed with 9 students, who were instructed to stay in their flats during the study days. A geofence was set for each alarm in the alerting system with a radius of 10 m (8 cases), 15 m (10 cases), and 20 m (9 cases) around the GPS position at which the alarm was accepted in the app. The system logged responders as being departed when the smartphone position was registered outside the geofence. The students were instructed to manually start a stopwatch at the time of the alert and to stop the stopwatch once they had entered the street in front of their flat. Results The median difference between automatically and manually retrieved times were −16 seconds [interquartile range IQR 50 seconds] (geofence 10 m), 30 seconds [IQR 25 seconds] (15 m), and 20 seconds [IQR 13 seconds] (20 m), respectively. The 20 m geofence was associated with the smallest interquartile range. Conclusion Departing times of volunteer responders in SAS can be retrieved automatically using GPS and a geofence

A non-enzymatic function of 17 beta-hydroxysteroid dehydrogenase type 10 is required for mitochondrial integrity and cell survival

Deficiency of the mitochondrial enzyme 2-methyl-3-hydroxybutyryl-CoA dehydrogenase involved in isoleucine metabolism causes an organic aciduria with atypical neurodegenerative course. The disease-causing gene is HSD17B10 and encodes 17beta-hydroxysteroid dehydrogenase type 10 (HSD10), a protein also implicated in the pathogenesis of Alzheimer's disease. Here we show that clinical symptoms in patients are not correlated with residual enzymatic activity of mutated HSD10. Loss-of-function and rescue experiments in Xenopus embryos and cells derived from conditional Hsd17b10(-/-) mice demonstrate that a property of HSD10 independent of its enzymatic activity is essential for structural and functional integrity of mitochondria. Impairment of this function in neural cells causes apoptotic cell death whilst the enzymatic activity of HSD10 is not required for cell survival. This finding indicates that the symptoms in patients with mutations in the HSD17B10 gene are unrelated to accumulation of toxic metabolites in the isoleucine pathway and, rather, related to defects in general mitochondrial function. Therefore alternative therapeutic approaches to an isoleucine-restricted diet are required

Durvalumab Plus Carboplatin/Paclitaxel Followed by Maintenance Durvalumab With or Without Olaparib as First-Line Treatment for Advanced Endometrial Cancer: The Phase III DUO-E Trial

PURPOSE Immunotherapy and chemotherapy combinations have shown activity in endometrial cancer, with greater benefit in mismatch repair (MMR)-deficient (dMMR) than MMR-proficient (pMMR) disease. Adding a poly(ADP-ribose) polymerase inhibitor may improve outcomes, especially in pMMR disease. METHODS This phase III, global, double-blind, placebo-controlled trial randomly assigned eligible patients with newly diagnosed advanced or recurrent endometrial cancer 1:1:1 to: carboplatin/paclitaxel plus durvalumab placebo followed by placebo maintenance (control arm); carboplatin/paclitaxel plus durvalumab followed by maintenance durvalumab plus olaparib placebo (durvalumab arm); or carboplatin/paclitaxel plus durvalumab followed by maintenance durvalumab plus olaparib (durvalumab + olaparib arm). The primary end points were progression-free survival (PFS) in the durvalumab arm versus control and the durvalumab + olaparib arm versus control. RESULTS Seven hundred eighteen patients were randomly assigned. In the intention-to-treat population, statistically significant PFS benefit was observed in the durvalumab (hazard ratio [HR], 0.71 [95% CI, 0.57 to 0.89]; P = .003) and durvalumab + olaparib arms (HR, 0.55 [95% CI, 0.43 to 0.69]; P < .0001) versus control. Prespecified, exploratory subgroup analyses showed PFS benefit in dMMR (HR [durvalumab v control], 0.42 [95% CI, 0.22 to 0.80]; HR [durvalumab + olaparib v control], 0.41 [95% CI, 0.21 to 0.75]) and pMMR subgroups (HR [durvalumab v control], 0.77 [95% CI, 0.60 to 0.97]; HR [durvalumab + olaparib v control] 0.57; [95% CI, 0.44 to 0.73]); and in PD-L1-positive subgroups (HR [durvalumab v control], 0.63 [95% CI, 0.48 to 0.83]; HR [durvalumab + olaparib v control], 0.42 [95% CI, 0.31 to 0.57]). Interim overall survival results (maturity approximately 28%) were supportive of the primary outcomes (durvalumab v control: HR, 0.77 [95% CI, 0.56 to 1.07]; P = .120; durvalumab + olaparib v control: HR, 0.59 [95% CI, 0.42 to 0.83]; P = .003). The safety profiles of the experimental arms were generally consistent with individual agents. CONCLUSION Carboplatin/paclitaxel plus durvalumab followed by maintenance durvalumab with or without olaparib demonstrated a statistically significant and clinically meaningful PFS benefit in patients with advanced or recurrent endometrial cancer

Advances in ILP-based Modulo Scheduling for High-Level Synthesis

In today's heterogenous computing world, field-programmable gate arrays (FPGA) represent the energy-efficient alternative to generic processor cores and graphics accelerators. However, due to their radically different computing model, automatic design methods, such as high-level synthesis (HLS), are needed to harness their full power. HLS raises the abstraction level to behavioural descriptions of algorithms, thus freeing designers from dealing with tedious low-level concerns, and enabling a rapid exploration of different microarchitectures for the same input specification. In an HLS tool, scheduling is the most influential step for the performance of the generated accelerator. Specifically, modulo schedulers enable a pipelined execution, which is a key technique to speed up the computation by extracting more parallelism from the input description. In this thesis, we make a case for the use of integer linear programming (ILP) as a framework for modulo scheduling approaches. First, we argue that ILP-based modulo schedulers are practically usable in the HLS context. Secondly, we show that the ILP framework enables a novel approach for the automatic design of FPGA accelerators. We substantiate the first claim by proposing a new, flexible ILP formulation for the modulo scheduling problem, and evaluate it experimentally with a diverse set of realistic test instances. While solving an ILP may incur an exponential runtime in the worst case, we observe that simple countermeasures, such as setting a time limit, help to contain the practical impact of outlier instances. Furthermore, we present an algorithm to compress problems before the actual scheduling. An HLS-generated microarchitecture is comprised of operators, i.e. single-purpose functional units such as a floating-point multiplier. Usually, the allocation of operators is determined before scheduling, even though both problems are interdependent. To that end, we investigate an extension of the modulo scheduling problem that combines both concerns in a single model. Based on the extension, we present a novel multi-loop scheduling approach capable of finding the fastest microarchitecture that still fits on a given FPGA device - an optimisation problem that current commercial HLS tools cannot solve. This proves our second claim

NoFTL-KV: tackling write-amplification on KV-stores with native storage management

Modern persistent Key/Value stores are designed to meet the demand for high transactional throughput and high data ingestion rates. Still, they rely on backwards-compatible storage stack and abstractions to ease space management, foster seamless proliferation and system integration. Their dependence on the traditional I/O stack has negative impact on performance, causes unacceptably high write-amplification, and limits the storage longevity. In the present paper we present NoFTL KV, an approach that results in a lean I/O stack, integrating physical storage management natively in the Key/Value store. NoFTL-KV eliminates backwards compatibility, allowing the Key/Value store to directly consume the characteristics of modern storage technologies. NoFTLKV is implemented under RocksDB. The performance evaluation under LinkBench shows that NoFTL-KV improves transactional throughput by 33%, while response times improve up to 2.3x. Furthermore, NoFTL KV reduces write-amplification 19x and improves storage longevity by imately the same factor