Optimal Performance of 16-bit Acyclic Adders of Binary Codes

The conducted studies established the prospect for enhancing the performance of computing components, specifically, combinational 16-bit adders, based on the use of the principles of computation of digital signals of an acyclic model.The application of an acyclic model for the synthesis of 16-bit parallel adders is designed for:– the process of sequential (for lower bits) and parallel (for all other bits) computation of the sum and carry signals. Thanks to this approach, it becomes possible to reduce eventually the complexity of the hardware part without increasing the circuit depth;– fixation (planning) of the adder circuit depth before its synthesis. This makes it possible to use the logical structure of transitive carry, which ensures the optimal adder circuit depth and does not increase its complexity.Utilizing an acyclic model for the construction of 16-bit parallel adders is more beneficial in comparison with the analogs by the following factors:– the lower cost development, since an acyclic model determines a simplerstructure of a 16-bit adder;– application of the latest developed logical structures of transitive carry,which makes it possible to decrease the delay of sum and carry signals, area, power consumption and to increase overall efficiency of 16-bit adders of binary codes.Due to this, the possibility of obtaining optimal values of structure complexity and the depth of the adder circuit is ensured. In comparison with the analogs, it provides an increase in quality of indicator of 16-bit acyclic adders, such as power consumption, chip area by 15–27 %, depending on the chosen structure, and performance by 10–60 %.There are some grounds to argue about the possibility of enhancing the performance of computing components, specifically, 16-bit adders of binary codes by using the principles of computation of digital signals of an acyclic model

Summation of Binary Codes Without Carry

The paper considers the operation of summation of binary codes in the scheme of a multi digit parallel adder without carry. The process of the operation of summation uses a pairing algorithm that provides for a logarithmic complexity to the algorithm of the calculation in the adder's scheme. Since the codes for the operation of summation, known in the literature, such as Galois field codes, the XAND codes, are defined by the systems of recurrent codes that contain one of the initial codes of complete combinatorial system with repetition, then the given codes are a particular case of the class of combinatorial systems of binary codes with a ring structure and initial code of complete combinatorial system with repetition. Therefore, the only basis of the mentioned systems of binary codes indicates the usefulness of their classification generalization, within the framework of the operation of summation, on the basis of a single criterion – an object of binary codes. Thus, the generalization of the classification of binary codes simplifies the structure of the subject area, increases the variety of systems of binary codes, in particular, for their application in arithmetic operations with binary numbers. It was established that the properties of the recurrent method of the synthesis of binary codes allow focusing the principle of building codes in the range of complete combinatorial system with repetition, which ensures reduction of the thesaurus of the parallel adder of binary codes without carry.The results of this study may be a component of the technology of designing electronic computing systems because:– they expand the apparatus of obtaining recurrent binary codes for their application in the information technology;– they provide a possibility to control the selection of the code at the stage of designing a computing device;– they help predict the impact of the implementation of the selected code for the solution of problems of the information systems..– they minimize hardware costs associated with the selection of the system of binary code for the calculation