System clock estimation based on clock wastage minimization

When synthesizing a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be specified in multiples of a clock cycle. In the absence of any tool to guide the selection of a clock cycle, a bad choice of the clock period could adversely affect the performance of the synthesized design. We present an algorithm for estimating the system clock based on a clock wastage minimization criteria. Limitations of previous approaches to the problem are discussed. The results obtained prove that the clock cycle estimated by the Clock Wastage Minimization method produce faster designs than previous solutions to the problem

An architecture for intelligent task interruption

In the design of real time systems the capability for task interruption is often considered essential. The problem of task interruption in knowledge-based domains is examined. It is proposed that task interruption can be often avoided by using appropriate functional architectures and knowledge engineering principles. Situations for which task interruption is indispensable, a preliminary architecture based on priority hierarchies is described

A test of local Lorentz invariance with Compton scattering asymmetry

We report on a measurement of the constancy and anisotropy of the speed of light relative to the electrons in photon-electron scattering. We used the Compton scattering asymmetry measured by the new Compton polarimeter in Hall~C at Jefferson Lab to test for deviations from unity of the vacuum refractive index ($n$). For photon energies in the range of 9 - 46 MeV, we obtain a new limit of $1-n < 1.4 \times 10^{-8}$. In addition, the absence of sidereal variation over the six month period of the measurement constrains any anisotropies in the speed of light. These constitute the first study of Lorentz invariance using Compton asymmetry. Within the minimal standard model extension framework, our result yield limits on the photon and electron coefficients $\tilde{\kappa}_{0^+}^{YZ}, c_{TX}, \tilde{\kappa}_{0^+}^{ZX}$, and $c_{TY}$. Although, these limits are several orders of magnitude larger than the current best limits, they demonstrate the feasibility of using Compton asymmetry for tests of Lorentz invariance. Future parity violating electron scattering experiments at Jefferson Lab will use higher energy electrons enabling better constraints.Comment: 7 pages, 5 figure

R. K. Narayanswami B.A.B.L. Engine Driver : Story-Telling and Memory in The Grandmother’s Tale, and Selected Stories

Much like the Nambi of this tale, R. K. Narayan has merited his reputation as a marvelous storyteller. Noted for his laser-beam focus on the closely-imagined Malgudi, he has come to be recognized as the Indian novelist, from whose pen many readers expected all the accumulated wisdom of the subcontinent\u27s abiding concern for transcendence. While such guru-ization amused Narayan, it also elicited his quietly sustained argument against procrustean templates by which the west insisted on reading him as typically Indian.

Synthesis from specifications : basic concepts

The need has evolved for a synthesis tool at the computer system level. SpecSyn is one such tool. Basically, it will view the world as a set of chips communicating via protocols. Thus, an abstract specification would get synthesized into a set of one or more interconnected chips. From that point, detail is added to each chip's specification until its structure is synthesized or it is determined that a prefabricated chip similar in functionality can be used.Features of such a tool include executable specifications from which to synthesize, constraint driven partitioning of the specifications into components (chips) and synthesis of interfaces between them, translation into VHDL and synthesis into VHDL structures of micro-architectural components, and the use of other tools (e.g. MILO, a micro-architecture and logic optimizer, and LES, a layout expert system) to evaluate the quality of the chip layout generated from VHDL description.A major component of SpecSyn is SpecCharts, a high level specification language amenable to system level synthesis, able to represent designs from system to register transfer levels. The language consists of a hierarchy of states, represented in combined graphical and textual form, at the same time catering to the expression of concurrent behavior and specification of constraints. With it we have specified several Intel chips as well as higher level systems, and have found it to be quite powerful and easy to use.SpecSyn will have a graphical interface, from which the user can at any time view or edit a SpecChart, translate to VHDL and simulate, view statistics provided by estimators (such as area, speed, and pins), store and retrieve SpecCharts, apply basic Spec Chart operations, as well as apply the partitioning algorithms or interface synthesizer. Providing access to a wide range of tools, having a single language represent the design throughout the synthesis process, and having user specified constraints allow the user to have varying amounts of control over the synthesis process