Are spin junction transistors suitable for signal processing?

A number of spintronic junction transistors, that exploit the spin degree of freedom of an electron in addition to the charge degree of freedom, have been proposed to provide simultaneous non-volatile storage and signal processing functionality. Here, we show that some of these transistors unfortunately may not have sufficient voltage and current gains for signal processing. This is primarily because of a large output ac conductance and poor isolation between input and output. The latter also hinders unidirectional propagation of logic signal from the input of a logic gate to the output. Other versions of these transistors appear to have better gain and isolation, but not better than those of a conventional transistor. Therefore, these devices may not improve state-of-the-art signal processing capability, although they may provide additional functionality by offering non-volatile storage. They may also have niche applications in non-linear circuits

Three-Dimensional MOS Process Development

A novel MOS technology for three-dimensional integration of electronic circuits on silicon substrates was developed. Selective epitaxial growth and epitaxial lateral overgrowth of monocrystalline silicon over oxidized silicon were employed to create locally restricted silicon-on-insulator device islands. Thin gate oxides were discovered to deteriorate in ambients typically used for selective epitaxial growth. Conditions of general applicability to silicon epitaxy systems were determined under which this deterioration was greatly reduced. Selective epitaxial growth needed to be carried out at low temperatures. However, crystalline defects increase as deposition temperatures are decreased. An exact dependence between the residual moisture content in epitaxial growth ambients, deposition pressure, and deposition temperature was determined which is also generally applicable to silicon epitaxy systems. The dependences of growth rates and growth rate uniformity on loading, temperature, flow rates, gas composition, and masking oxide thickness were investigated for a pancake type epitaxy reactor. A conceptual model was discussed attempting to describe the effects peculiar to selective epitaxial growth. The newly developed processing steps were assembled to fabricate three dimensional silicon-on-insulator capacitors. These capacitors were electrically evaluated. Surface state densities were in the order of 1O11cm-2 eV-1 and therefore within the range of applicability for a practical CMOS process. Oxidized polysilicon gates were overgrown with silicon by epitaxial lateral overgrowth. The epitaxial silicon was planarized and source and drain regions were formed above the polysilicon gates in Silicon-on-insulator material. The modulation of the source-drain current by bias changes of the buried gate was demonstrated

Evaluation of Silicon Selective Epitaxial Growth Defects using the Sidewall Gate Controlled Diode

Selective Epitaxial Growth (SEG) of silicon has shown great potential for advanced integrated circuit technologies. Before SEG can be fully utilized, sidewall defects must be reduced or at least controlled. The phenomena responsible for these defects were not understood, therefore more quantification of the sidewall defects is necessary. Walled diodes have been used to measure the sidewall leakage currents, but are susceptible to problems which make them poor devices for comparing different sidewall interfaces. A new device structure, the Sidewall Gate Controlled Diode (SGCD), is presented for the quantification of the defects near the SEG sidewall. The SGCD is shown to have advantages over the use of walled diodes despite the complex fabrication process required to build it. The development of the fabrication process for this device and the verification of its useful operation are presented. After the operation of the SGCD was verified, the device was used to evaluate the effects of various SEG deposition parameters on the sidewall defect density. This study determined that lower temperature, slower growth rate depositions followed with an in-situ hydrogen anneal generally reduced the defect density. Inconsistencies in the results also indicated that the profile of the sidewall may also influence the defect density at the SEG/oxide sidewall

Temperature Distribution Within a Defect-Free Silicon Carbide Diode Predicted by a Computational Model

Most solid-state electronic devices diodes, transistors, and integrated circuits are based on silicon. Although this material works well for many applications, its properties limit its ability to function under extreme high-temperature or high-power operating conditions. Silicon carbide (SiC), with its desirable physical properties, could someday replace silicon for these types of applications. A major roadblock to realizing this potential is the quality of SiC material that can currently be produced. Semiconductors require very uniform, high-quality material, and commercially available SiC tends to suffer from defects in the crystalline structure that have largely been eliminated in silicon. In some power circuits, these defects can focus energy into an extremely small area, leading to overheating that can damage the device. In an effort to better understand the way that these defects affect the electrical performance and reliability of an SiC device in a power circuit, the NASA Glenn Research Center at Lewis Field began an in-house three-dimensional computational modeling effort. The goal is to predict the temperature distributions within a SiC diode structure subjected to the various transient overvoltage breakdown stresses that occur in power management circuits. A commercial computational fluid dynamics computer program (FLUENT-Fluent, Inc., Lebanon, New Hampshire) was used to build a model of a defect-free SiC diode and generate a computational mesh. A typical breakdown power density was applied over 0.5 msec in a heated layer at the junction between the p-type SiC and n-type SiC, and the temperature distribution throughout the diode was then calculated. The peak temperature extracted from the computational model agreed well (within 6 percent) with previous first-order calculations of the maximum expected temperature at the end of the breakdown pulse. This level of agreement is excellent for a model of this type and indicates that three-dimensional computational modeling can provide useful predictions for this class of problem. The model is now being extended to include the effects of crystal defects. The model will provide unique insights into how high the temperature rises in the vicinity of the defects in a diode at various power densities and pulse durations. This information also will help researchers in understanding and designing SiC devices for safe and reliable operation in high-power circuits

A New Method to Grow SiC: Solvent-Laser Heated Floating Zone

The solvent-laser heated floating zone (solvent-LHFZ) growth method is being developed to grow long single crystal SiC fibers. The technique combines the single crystal fiber growth ability of laser heated floating zone with solvent based growth techniques (e.g. traveling solvent method) ability to grow SiC from the liquid phase. Initial investigations reported in this paper show that the solvent-LHFZ method readily grows single crystal SiC (retains polytype and orientation), but has a significant amount of inhomogeneous strain and solvent rich inclusions

Experiments in Interrupted Growth Molecular Beam Epitaxy Technology

From a device structure standpoint it would be advantageous to sandwich laterally defined features between layers of epitaxially grown material. In silicon this is commonly dope by growing the bottom layer, patterning the desired feature, and growing a second layer. Unfortunately, this process has not been practical in GaAs for the same reason that there is no true MOS technology in GaAs: The. GaAs surface is irreparably damaged when it is exposed to the atmosphere leading to the formation of undesirable interface states. Heterojunction FET\u27s are feasible only because high quality epilayers are grown during a single run in an ultrahigh vacuum environment. Standard growth methods allow for variation of doping and material content only in one direction, normal to the wafer surface. Varying the material in more than one dimension without the use of prohibitively exotic equipment requires removal of the wafer from the growth apparatus for lateral processing between material growths. Thus the problem that this thesis attempts to address: How to protect a GaAs surface during a lateral processing step and initiate regrowth leaving behind an electrically invisible restart interface. The potential applications of the development of a successful interrupted growth scheme for GaAs are numerous and far reaching. Specifically it would allow the fabrication of advantageous device geometries that are not possible under single material growth runs. Although this thesis deals exclusively with ion implanted interrupted growth by Molecular Beam Epitaxy, some of the concepts arid theories can be extended to other growth methods. It is both a review of previous work and a report of our attempts at Purdue to fabricate the first interrupted growth HIGFET\u27s and MISFET\u27s. Mechanisms behind the success and failure of GaAs interrupted growth are discussed and several experiments involving passivation materials and new interrupted growth schemes are propose

Valence band structure and band offset of 3C- and 4H-SiC studied by ballistic hole emission microscopy

p-type Schottky barriers in Pt/3C-SiC contacts have been measured using ballistic hole emission microscopy (BHEM) and estimated to be ???0.06 eV higher than identically prepared Pt/p-type 4H-SiC contacts. This indicates the 3C-SiC valence band maximum (VBM) is ???0.06 eV below the 4H-SiC VBM, consistent with the calculated ???0.05 eV type-II valence band offset between these polytypes. We also observe no evidence of an additional VBM in 3C-SiC, which supports the proposal that the second VBM observed in BHEM spectra on 4H-SiC is a crystal-field split VBM located ???110 meV below the highest VBM.open6

Characterization of 4H <000-1> Silicon Carbide Films Grown by Solvent-Laser Heated Floating Zone

Commercially available bulk silicon carbide (SiC) has a high number (>2000/sq cm) of screw dislocations (SD) that have been linked to degradation of high-field power device electrical performance properties. Researchers at the NASA Glenn Research Center have proposed a method to mass-produce significantly higher quality bulk SiC. In order for this bulk growth method to become reality, growth of long single crystal SiC fibers must first be achieved. Therefore, a new growth method, Solvent-Laser Heated Floating Zone (Solvent-LHFZ), has been implemented. While some of the initial Solvent-LHFZ results have recently been reported, this paper focuses on further characterization of grown crystals and their growth fronts. To this end, secondary ion mass spectroscopy (SIMS) depth profiles, cross section analysis by focused ion beam (FIB) milling and mechanical polishing, and orientation and structural characterization by x-ray transmission Laue diffraction patterns and x-ray topography were used. Results paint a picture of a chaotic growth front, with Fe incorporation dependant on C concentration

A New Method to Grow SiC: Solvent-Laser Heated Floating Zone

The solvent-laser heated floating zone (solvent-LHFZ) growth method is being developed to grow long single crystal SiC fibers. The technique combines the single crystal fiber growth ability of laser heated floating zone with solvent based growth techniques (e.g. traveling solvent method) ability to grow SiC from the liquid phase. Initial investigations reported in this paper show that the solvent-LHFZ method readily grows single crystal SiC (retains polytype and orientation), but has a significant amount of inhomogeneous strain and solvent rich inclusions

Growth and Characterization of 3C-SiC and 2H-AIN/GaN Films and Devices Produced on Step-Free 4H-SiC Mesa Substrates

While previously published experimental results have shown that the step-free (0 0 0 1) 4H-SiC mesa growth surface uniquely enables radical improvement of 3C-SiC and 2H-AlN/GaN heteroepitaxial film quality (greater than 100-fold reduction in extended defect densities), important aspects of the step-free mesa heterofilm growth processes and resulting electronic device benefits remain to be more fully elucidated. This paper reviews and updates recent ongoing studies of 3C-SiC and 2H-AlN/GaN heteroepilayers grown on top of 4H-SiC mesas. For both 3C-SiC and AlN/GaN films nucleated on 4H-SiC mesas rendered completely free of atomic-scale surface steps, TEM studies reveal that relaxation of heterofilm strain arising from in-plane film/substrate lattice constant mismatch occurs in a remarkably benign manner that avoids formation of threading dislocations in the heteroepilayer. In particular, relaxation appears to occur via nucleation and inward lateral glide of near-interfacial dislocation half-loops from the mesa sidewalls. Preliminary studies of homojunction diodes implemented in 3C-SiC and AlN/GaN heterolayers demonstrate improved electrical performance compared with much more defective heterofilms grown on neighbouring stepped 4H-SiC mesas. Recombination-enhanced dislocation motion known to degrade forward-biased 4H-SiC bipolar diodes has been completely absent from our initial studies of 3C-SiC diodes, including diodes implemented on defective 3C-SiC heterolayers grown on stepped 4H-SiC mesas