FPgrep and FPsed: Packet Payload Processors for Managing the Flow of Digital Content on Local Area Networks and the Internet

As computer networks increase in speed, it becomes difficult to monitor and manage the transmitted digital content. To alleviate these problems, hardware-based search (FPgrep) and search-and-replace (FPsed) modules have been developed. FP-grep has the ability to scan packet payloads for a given set of regular expressions and pass or drop packets based on the payload contents. FPsed also scans packet payloads for a set of regular expressions and adds the ability to modify the payload if desired. The hardware circuits that implement the FPgrep and FPsed modules can be generated, compiled, and synthesized using a simple web interface. Once a module is created it is programmed into logic on a Field Programmable Gate Array (FPGA). The FPgrep and FPsed modules use FPGAs to process packets at the full rate of Gigabit-speed networks. Both modules, along with several supporting applications were developed and tested using the Field Programmable Port Extender (FPX) platform. Applications developed for the modules currently include a spam filter, virus protection, an information security filter, as well as a copyright enforcement function

Cross-sectional prevalence of SARS-CoV-2 antibodies in healthcare workers in paediatric facilities in eight countries

Funding Information: DG receives support from the NIHR Great Ormond Street Biomedical Research Centre . HZ is supported by the South African Medical Research Council . Publisher Copyright: © 2021 The Author(s)Background: Healthcare workers (HCWs) have been disproportionately affected by coronavirus disease 2019 (COVID-19), which may be driven, in part, by nosocomial exposure. If HCW exposure is predominantly nosocomial, HCWs in paediatric facilities, where few patients are admitted with COVID-19, may lack antibodies to severe acute respiratory syndrome coronavirus-2 (SARS-CoV-2) and be at increased risk during the current resurgence. Aim: To compare the seroprevalence of SARS-CoV-2 amongst HCWs in paediatric facilities in seven European countries and South Africa (N=8). Methods: All categories of paediatric HCWs were invited to participate in the study, irrespective of previous symptoms. A single blood sample was taken and data about previous symptoms were documented. Serum was shipped to a central laboratory in London where SARS-CoV-2 immunoglobulin G was measured. Findings: In total, 4114 HCWs were recruited between 1st May and mid-July 2020. The range of seroprevalence was 0–16.93%. The highest seroprevalence was found in London (16.93%), followed by Cape Town, South Africa (10.36%). There were no positive HCWs in the Austrian, Estonian and Latvian cohorts; 2/300 [0.66%, 95% confidence interval (CI) 0.18–2.4] HCWs tested positive in Lithuania; 1/124 (0.81%, 95% CI 0.14–4.3) HCWs tested positive in Romania; and 1/76 (1.3%, 95% CI 0.23–7.0) HCWs tested positive in Greece. Conclusion: Overall seroprevalence amongst paediatric HCWs is similar to their national populations and linked to the national COVID-19 burden. Staff working in paediatric facilities in low-burden countries have very low seroprevalence rates and thus are likely to be susceptible to COVID-19. Their susceptibility to infection may affect their ability to provide care in the face of increasing cases of COVID-19, and this highlights the need for appropriate preventative strategies in paediatric healthcare settings.publishersversionPeer reviewe

A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing

This paper presents a reconfigurable architecture for high-speed content-based routing. Our architecture goes beyond simple pattern matching by implementing a parsing engine that defines the semantics of patterns that are parsed within the data stream. Defining the semantics of patterns allows for more accurate processing and routing of packets using any fields that appear within the payload of the packet. The architecture consists of several components, including a pattern matcher, a parsing structure, and a routing module. Both the pattern matcher and parsing structure are automatically generated using an application-specific compiler that is described in this paper. The compiler accepts a grammar specification as input and outputs a data parser in VHDL. The routing module receives control signals from both the pattern matcher and the parsing structure that aid in the routing of packets. We illustrate how a content-based router can be implemented with our technique using an XML parser as an example. The XML parser presented was designed, implemented, and tested in a Xilinx Virtex XCV2000E FPGA on the FPX platform. It is capable of processing 32-bits of data per clock cycle and runs at 100 MHz. This allows the system to process and route XML messages at 3.2 Gbps