Optimizing the FPGA memory design for a Sobel edge detector

This paper explores different memory systems by investigating the trade-offs involved with choosing one memory system over another on an FPGA. As an example, we use a Sobel edge detector to look at the trade-offs for different memory components. We demonstrate how each type of memory affects I/O performance and area. By exploiting these trade-offs in performance and area a designer should be able to find an optimum on-chip memory system for a given application

Optimizing the FPGA memory design for a Sobel edge detector

This research explored different memory systems on FPGA chips in order to show the various trade-offs involved with choosing one memory system over another. We explored the different memory components that are found on FPGA chips using the example of a Sobel edge detector. We demonstrated how the different FPGA chip’s memories affected I/O performance and area. By exploiting the trade-offs between these a designer should be able to find an optimal on-chip memory system for a given application. Given further study, we believe we can develop application-specific memory templates that can be used with a hardware compiler to generate optimal on-chip memory system

Developing memory templates for high level synthesis compilers

We are investigating parametrized memory templates for use with high level synthesis compilers. Each template would have parameters that reflect important trade-offs made during system design, and can be interfaced with external block random access memory (BRAM). The templates would incorporated in our high level synthesis (HLS) compiler, where the template's parameters are adjusted to the application and hardware. Each template would be designed to suite a different type of application. For example we have already made one template for use with a parallel 'for' loops with no loop dependencies and sequential bodies. In the future, we will develop more templates for other types of 'for' loops. We will enhance the compiler so that it can identify the type of application it is compiling and recommend the template best suited for it. The candidate templates will be selected by first matching them against the application's data access pattern with the final decision made using design space exploration of each candidate to find the one with the best performance characteristics

A parallel for loop memory template for a high level synthesis compiler

We propose a parametrized memory template for applications with parallel 'for' loops. The template's parameters reflect important trade-offs made during system design. The template is incorporated in our high level synthesis (HLS) compiler, where the template's parameters are adjusted to the application. The template fits parallel 'for' loops with no loop dependencies and sequential bodies. We found two alternative template implementations using our compiler. In the future, we will develop templates for other types of 'for' loops. These will be added to the compiler and it will identify the template that works best for the application it is compiling. Once a template is selected, the compiler will use design space exploration to select the best combination of template parameters for the targeted hardware and application