This research explored different memory systems on FPGA chips in order to show the various trade-offs involved with choosing one memory system over another. We explored the different memory components that are found on FPGA chips using the example of a Sobel edge detector. We demonstrated how the different FPGA chip’s memories affected I/O performance and area. By exploiting the trade-offs between these a designer should be able to find an optimal on-chip memory system for a given application. Given further study, we believe we can develop application-specific memory templates that can be used with a hardware compiler to generate optimal on-chip memory system

Devos, Harald

Moore, Craig Truett

Stroobandt, Dirk

Ghent University Academic Bibliography

Optimizing the FPGA Memory Designfor a Sobel Edge DetectorCraig Moore, Harald Devos and Dirk StroobandtHardware and Embedded Systems GroupElectronics and Information Systems DepartmentGhent University, Belgiumphone +32 9 264 33 66 | fax +32 9 264 35 94{craig.moore, harald.devos, dirk.stroobandt}@elis.ugent.beIndex Terms—Field programmable gate arrays, Memories,Memory architecture, BuffersAbstract—This research explored different memory systemson FPGA chips in order to show the various trade-offs involvedwith choosing one memory system over another. We exploredthe different memory components that are found on FPGA chipsusing the example of a Sobel edge detector. We demonstrated howthe different FPGA chip’s memories affected I/O performanceand area. By exploiting the trade-offs between these a designershould be able to find an optimal on-chip memory system for agiven application. Given further study, we believe we can developapplication-specific memory templates that can be used with ahardware compiler to generate optimal on-chip memory systems.I. INTRODUCTIONApplication specific hardware designs enjoy exponentialgains in computation speed, compared to equivalent softwaredesigns, since they can take advantage of the highly parallelnature of their architecture. Hardware designers are free toutilize the hardware that runs their applications in any way theychoose. However, this makes the size of their problem spacemuch larger since they have more considerations related tohardware selection. The same is not true for software designerssince many of the hardware considerations are handled by thecompiler. We believe our research is important in this regard,since hardware compilers (or high level synthesis tools) arenot yet able to efficiently choose the correct memory systemfor an application without significant human intervention. Fur-thermore, since the memory system can be a major bottleneckin system performance, it is important that hardware compilersbe able to select the optimum on-chip memory system for agiven application.II. METRICSThere are four important metrics for hardware designs whenit comes to memory: bandwidth, latency, size, and area. Usinga traditional pipeline analogy, bandwidth would be the size(flow rate) of the pipe or the number of pipes used. Latencycan be described as the length of the pipe(s). The longer thepipe, the longer it takes for the data to reach its destinationand the slower the overall system. If items can be stored neartheir destination, then they will not need to be retrieved furtherupstream which reduces the overall execution time. This iswhy size is an important metric. If there is insufficient space tostore all the values needed, then the system must replace stalevalues for new ones when needed. A well designed memorysystem should only replace those values that are no longerneeded in order to minimize (or eliminate) multiple calls toexternal memory for the same value. Often, the larger thesize of the memory required means a larger area occupiedin hardware so area is also an important consideration.There are typically three different types of memory avail-able: registers, block memory (RAM), and external memory.As seen in Table I, each memory type has its own benefits anddrawbacks. Registers are fast, but are evenly distributed on theFPGA so consume a larger amount of area when connectedtogether to form a larger memory system. Block RAM on theFPGA, while slower than registers, is much more compactallowing it to occupy less area on the FPGA by comparison.External RAM, is much larger than the other two and occupiesno space on the FPGA. However, it is much slower since datahas to travel further to reach its destination.TABLE I: Proposed taxonomy of trade-offs.Type Latency Bandwidth Size Arearegisters ++ ++ ± – –block memory + + ± +external memory – – – ++ ++± Depends on FPGA architecture selectedIII. EXPLORATION OF MEMORY SYSTEMSWe explored the trade-offs between memory componentsusing a Sobel edge detector because it offers a number ofopportunities for data reuse, prefetching, and parallel access.The Sobel edge detector example is also similar to a numberof other applications that use windowing operations, such asa FIR filter and wavelet transforms [1]. Sobel edge detectorsare used in image processing to identify and isolate areas onan image with strong intensity changes from one pixel to thenext.We developed four designs which each have a different typeof memory system to demonstrate the trade-offs in perfor-mance and area. Each design consisted of four components:an input buffer, the data path, an output buffer, and a simulated-496-input buffer data path output bufferwereadyq00q01q02q10q12q20q21q22d wed00d01d02d10d12d20d21d22readyqwed readyqmemorywedreadyqFig. 1: System configuration used for each designexternal memory as shown in Fig. 1. The designs each use adifferent type of input buffer, but have the same data pathwith a slightly different output buffer in each design. The firstdesign uses primarily external memory and a very small inputbuffer of eight registers for the sliding window. The remainingdesigns all have input and output buffers that are able to reusevalues without having to reread them from external memory.The second design’s input buffer uses only registers and noblock RAM. The third design’s input buffer uses primarilyblock RAM, and the fourth design uses a combination of blockRAM with registers.After simulating each design, we verified that it producesthe same output images as the C code which we based ourdesigns on [2] and synthesized it using Altera’s Quartus IIVersion 8.0 targeting a Stratix EP1S25F1020C5 board. Theresults are shown in Table II.A. External MemoryXY Register in WindowSliding Window BufferImage PixelPixel to be calculated11KeyYX0123M-1.  .  .0 1 2 3 N-1.  .  ..  .  .000102101112202122.  .  ..  .  ..  .  ..  .  ..  .  ..  .  ..  .  ..  .  ..  .  ..  .  .Input ImageFig. 2: External memory design: input image withinput buffer registers centered at pixel 2,2The first design listed in Table II consists of a small inputbuffer of eight registers where each register stores one pixelin the sliding window, as show in Fig. 2. Before the data pathcan begin calculating the first window, the input buffer mustread eight pixels. Pixels are read in from external memoryeach time they are needed so there is no way to reuse pixelsafter they are used. As can be seen in the table of results, thisdesign has the fastest clock speed, utilizes the least amount ofresources on the FPGA, but has the longest execution time.This long execution time is due to the fact that no pixels arereused.B. Registers with Data ReuseInput Image0 1 2 3 N-1Input Pixel StreamYX.  .  .0001021011122021223 N-1.  .  .3 N-1.  .  .Input BufferShift RegistersSliding WindowRegistersFig. 3: Registers with Data Reuse: Input bufferusing registers organized as a shift registerWe can reduce the number of execution cycles by addingmore registers to the input buffer so that pixels can be storedand reused until they are no longer needed. We did this byadding shift registers, as shown in Fig. 3 where values areread in sequentially from the input image as a stream of inputpixels. The input buffer stores two rows of pixels from theinput image and top three pixels of the sliding window. Valuesare then shifted through the sliding windows as shown by thearrows. When pixels are no longer needed they are simplyshifted out of the input buffer. Before the data path can startprocessing the input buffer must first read in the first tworows and three pixels from the third row. Overall this was thefastest design compared with the others because it required thefewest number of execution cycles with almost the same clockspeed as external memory design. However, because the inputbuffer is composed entirely of registers, which are distributeduniformly over the FPGA, it utilized the largest area on theFPGA.C. Block RAM with Data ReuseWe can reduce the area utilized by using block RAM insteadof registers in the input buffer as show in Fig. 4. However,this design has a longer pipeline latency because calculationcan only start once the first three rows of the input imagehave been buffered. While having a slower clock speed and alarger number of execution cycles, this design utilized a muchsmaller area on the FPGA.-497-TABLE II: Table of Synthesis Results for each design.Design Frequency Cycles1 Time1,2 Area1,3 Registers1 RAM1,4 Accesses1,5 Bandwidth1,61 142.82 MHz 810,275 5.67 ms 187 91 0 bits 808,992 142.93 B/s2 139.80 MHz 102,726 0.73 ms 5,474 5,322 0 bits 102,400 140.27 B/s3 123.20 MHz 104,000 0.84 ms 459 252 7,584 bits 102,400 121.30 B/s4 134.73 MHz 103,683 0.77 ms 492 260 5,056 bits 102,400 133.06 B/s1. Values when used with a 320× 320 pixel, 8-bit encoded bitmap input image2. Execution time = cycles/frequency3. The total number of logic elements utilized by the design4. Bits of on-chip RAM memory blocks utilized5. Number of accesses to external memory made by the design6. Required external memory bandwidth =`memory accesses · (bytes/access)´/timeYX221202Sliding WindowN-1N-1.  .  ..  .  .Input BufferBlock RAMs2111010 1 2 3 N-1. . .Input Pixel Stream3N-1.  .  .201000 33Input ImageFig. 4: Block RAM with Data Reuse: Input buffer using blockRAM organized as a shift registerD. Block RAM and Registers with Data ReuseThe final design is a combination of the register designwith the block RAM design as seen in Fig. 5. This designhas almost the same performance as the register design andutilizes almost the same area as the block RAM design. Asshow in Table II, this design makes the best trade-off betweenarea and performance compared with the other three designs.IV. RELATED WORKMany current hardware compiler projects can convert highlevel programming languages like C to a hardware descrip-tion language (HDL) for FPGAs [3]–[11]. Part of this workinvolves developing the memory systems to be used for theapplications it compiles. One component of this is identifyingthe design patterns of the application. A survey of suchwork can be found in [12]. Another component is developingthe memory systems which are best suited for a particularapplication [13], [14], so that once the design pattern of theapplication is identified the compiler can pair it with thememory system best suited for that application. Our work hasshown how important exploration of an application’s memorysystem can be on performance.000102101112202122Sliding WindowRegistersInput BufferBlock RAMsInput Image0 1 2 3 N-1Input Pixel StreamYX.  .  .N-1.  .  .3N-1.  .  .3Fig. 5: Block RAM and Registers with Data Reuse: Input bufferusing block RAM and registers organized as a shift registerDong et al. proposed a universal memory structure to beused within high level synthesis of sliding window appli-cations [14]. During our exploration, we utilized a similarmemory structure to their system, as described in section III-D,with registers for the window pixels and block memory forbuffering values from external memory. However, their designuses three rows of pixels in block memory while ours onlyrequires two rows. Additionally, their system uses a dataflowcontroller in between the window registers and buffer memory.We do not need this because the values for the window areshifted into place without a controller’s intervention. Theyhave better clock speeds than our design, but without furtherinfo regarding their memory block utilization numbers we cannot make a direct comparison.Guo et al. also developed a buffer which uses input datareuse in window operations [1] and further extended it forsimplified loop control [7]. We have found that their smartbuffer can’t hold enough values without having to rereadvalues from external memory. However, the benefit of theirbuffer is that, like ours, a dataflow controller is not required.A point not addressed in this paper, but important to be-498-aware of, is the problem of interfacing with external memory.Diniz et al. [15], [16] state that most designs do not interfacedirectly with external memory, rather they use vendor-specificIP cores that have interface signals which can be utilizedby the on-chip memory system. In their implementation ofthe DEFACTO compilation and synthesis system, they definetwo interfaces and a set of parameterizable abstractions tointerface with existing synthesis tools. Using this type ofimplementation ensures that they can still use application-specific scheduling. They do this by using distinct orderingof memory accesses which interfaces with the vendor-specificmemory IP core that handles the access to external memory.Since this is a fixed cost for any design, we did not take it intoconsideration, but in future work we will investigate it furtherto see if there may be optimizations to be exploited.V. CONCLUSIONS AND FUTURE WORKWe found that a combination of registers and block memoryworked best for a Sobel edge detector because it makes thebest trade-off between area and performance. It used a typeof smart buffer that shifts values into the sliding window,without having to reread values from memory. We believe thisdesign could be used with a hardware compiler and may bean improvement over the memory systems developed in [1],[14].Future work will include, incorporating our memory designinto the JCCI compiler developed by Devos et al. [17]. Wewill develope a parameterizable version of our memory designthat can be easily adapted to the size of the system. Then wewill look at how it performs with other applications usingour compiler. We also want to investigate other performancemetrics such as power and data locality like the work done byCathoor et al [18]. Finally, we will be investigating addingan external memory controller that can be adapted to suitvendor-specific IP memory interfaces like the one used by theDEFACTO compiler [15].VI. ACKNOWLEDGMENTSThis research is supported by the I.W.T. grant 060068.Ghent University is a member of the HiPEAC Network ofExcellence. The authors would like to thank Karel Bruneeland Wim Meeus for their valuable suggestions.REFERENCES[1] Z. Guo, B. Buyukkurt, and W. Najjar, “Input data reuse incompiling window operations onto reconfigurable hardware,” in LCTES’04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference onLanguages, Compilers, and Tools for Embedded Systems. ACM Press,July 2004, pp. 249–256. [Online]. Available: http://www.cs.ucr.edu/∼zguo/[2] B. Green, “Edge detection tutorial,” http://www.pages.drexel.edu/∼weg22/edge.html, 2002, last Accessed 2009.02.24.[3] Mentor Graphics, “Catapult C synthesis,” http://www.mentor.com/products/esl/high level synthesis/catapult synthe%sis/, Accessed01.2009.[4] S. Gupta, R. Gupta, N. Dutt, and A. Nicolau, SPARK, A ParallelizingApproach to the High-Level Synthesis of Digital Circuits. KluwerAcademic Publishers, 2004.[5] Agility (Formerly Celoxica), “Handel-C,” February 2009. [On-line]. Available: http://www.agilityds.com/products/c based products/dk design suite/hand%el-c.aspx[6] Impulse Accelerated Technologies, “Impulse C,” http://www.impulsec.com/, Accessed 01.2009.[7] Z. Guo, W. Najjar, and B. Buyukkurt, “Efficient hardware codegeneration for FPGAs,” ACM Trans. Archit. Code Optim., vol. 5,no. 1, pp. 1–26, May 2008. [Online]. Available: http://www.cs.ucr.edu/\∼zguo/papers/TACO manuscript.pdf[8] F. Diet, E. H. D’Hollander, K. Beyls, and H. Devos, “Embeddingsmart buffers for window operations in a stream-oriented C-to-VHDLcompiler,” in 4th IEEE International Symposium on Electronic Design,Test & Applications (DELTA’08), Hong Kong, January 2008, pp. 142–147.[9] D. Ghica, “Function interface models for hardware compilation,”School of Computer Science, University of Birmingham, UK,drg@cs.bham.ac.uk, Technical Report CSR-08-04, November 2008.[10] B. So, M. W. Hall, and H. E. Ziegler, “Custom data layout for memoryparallelism,” in CGO ’04: Proceedings of the international symposiumon Code generation and optimization. Washington, DC, USA: IEEEComputer Society, 2004, p. 291.[11] M. Bednara and J. Teich, “Automatic synthesis of FPGA processorarrays from loop algorithms.” Journal of Supercomputing, vol. 26, no. 2,pp. 149–165, September 2003.[12] A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi,M. Vanier, and M. Wrighton, “Design patterns for reconfigurablecomputing,” in 12th Annual IEEE Symposium on Field-ProgrammableCustom Computing Machines, FCCM, April 2004, pp. 13–23.[13] H. Devos, “Loop transformations for the optimized generation of re-configurable hardware,” Ph.D. dissertation, Ghent University, February2008.[14] Y. Dong, Y. Dou, and J. Zhou, “Optimized generation of memorystructure in compiling window operations onto reconfigurable hardware,”in International Workshop on Applied Reconfigurable Computing (ARC),ser. Lecture Notes in Computer Science, vol. 4419, 2007, pp. 110–121.[15] J. Park and P. C. Diniz, “Synthesis of pipelined memory accesscontrollers for streamed data applications on FPGA-based computingengines,” in ISSS ’01: Proceedings of the 14th international symposiumon Systems synthesis. New York, NY, USA: ACM, 2001, pp. 221–226. [Online]. Available: http://www.isi.edu/∼pedro/PUBLICATIONS/isss2001.html[16] P. Diniz, M. Hall, J. Park, B. So, and H. Ziegler, “Automatic mappingof C to FPGAs with the DEFACTO compilation and synthesis system,”Microprocessors and Microsystems, vol. 29, no. 2-3, pp. 51–62, April2005.[17] H. Devos, W. Meeus, and D. Stroobandt, “CLooGVHDL and JCCI,” inDATE University Booth, Nice, France, April 2009, pp. 1–2 (CD–ROM).[18] F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele,and A. Vandecappelle, Custom Memory Management Methodology:Exploration of Memory Organisation for Embedded Multimedia SystemDesign. Boston, USA: Kluwer Academic Publishers, 1998.-499-

Optimizing the FPGA memory design for a Sobel edge detector

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Optimizing the FPGA memory design for a Sobel edge detector

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