96 research outputs found
Near-thermal limit gating in heavily-doped III-V semiconductor nanowires using polymer electrolytes
Doping is a common route to reducing nanowire transistor on-resistance but
has limits. High doping level gives significant loss in gate performance and
ultimately complete gate failure. We show that electrolyte gating remains
effective even when the Be doping in our GaAs nanowires is so high that
traditional metal-oxide gates fail. In this regime we obtain a combination of
sub-threshold swing and contact resistance that surpasses the best existing
p-type nanowire MOSFETs. Our sub-threshold swing of 75 mV/dec is within 25% of
the room-temperature thermal limit and comparable with n-InP and n-GaAs
nanowire MOSFETs. Our results open a new path to extending the performance and
application of nanowire transistors, and motivate further work on improved
solid electrolytes for nanoscale device applications.Comment: 6 pages, 2 figures, supplementary available at journa
The influence of atmosphere on the performance of pure-phase WZ and ZB InAs nanowire transistors
We compare the characteristics of phase-pure MOCVD grown ZB and WZ InAs
nanowire transistors in several atmospheres: air, dry pure N and O, and
N bubbled through liquid HO and alcohols to identify whether
phase-related structural/surface differences affect their response. Both WZ and
ZB give poor gate characteristics in dry state. Adsorption of polar species
reduces off-current by 2-3 orders of magnitude, increases on-off ratio and
significantly reduces sub-threshold slope. The key difference is the greater
sensitivity of WZ to low adsorbate level. We attribute this to facet structure
and its influence on the separation between conduction electrons and surface
adsorption sites. We highlight the important role adsorbed species play in
nanowire device characterisation. WZ is commonly thought superior to ZB in InAs
nanowire transistors. We show this is an artefact of the moderate humidity
found in ambient laboratory conditions: WZ and ZB perform equally poorly in the
dry gas limit yet equally well in the wet gas limit. We also highlight the
vital role density-lowering disorder has in improving gate characteristics, be
it stacking faults in mixed-phase WZ or surface adsorbates in pure-phase
nanowires.Comment: Accepted for publication in Nanotechnolog
Towards low-dimensional hole systems in Be-doped GaAs nanowires
GaAs was central to the development of quantum devices but is rarely used for
nanowire-based quantum devices with InAs, InSb and SiGe instead taking the
leading role. p-type GaAs nanowires offer a path to studying strongly-confined
0D and 1D hole systems with strong spin-orbit effects, motivating our
development of nanowire transistors featuring Be-doped p-type GaAs nanowires,
AuBe alloy contacts and patterned local gate electrodes towards making
nanowire-based quantum hole devices. We report on nanowire transistors with
traditional substrate back-gates and EBL-defined metal/oxide top-gates produced
using GaAs nanowires with three different Be-doping densities and various AuBe
contact processing recipes. We show that contact annealing only brings small
improvements for the moderately-doped devices under conditions of lower anneal
temperature and short anneal time. We only obtain good transistor performance
for moderate doping, with conduction freezing out at low temperature for
lowly-doped nanowires and inability to reach a clear off-state under gating for
the highly-doped nanowires. Our best devices give on-state conductivity 95 nS,
off-state conductivity 2 pS, on-off ratio ~, and sub-threshold slope 50
mV/dec at T = 4 K. Lastly, we made a device featuring a moderately-doped
nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a
plateau in the sub-threshold region that is reproducible in separate cool-downs
and indicative of possible conductance quantization highlighting the potential
for future quantum device studies in this material system
Using polymer electrolyte gates to set-and-freeze threshold voltage and local potential in nanowire-based devices and thermoelectrics
We use the strongly temperature-dependent ionic mobility in polymer
electrolytes to 'freeze in' specific ionic charge environments around a
nanowire using a local wrap-gate geometry. This enables us to set both the
threshold voltage for a conventional doped substrate gate and the local
disorder potential at temperatures below 200 Kelvin, which we characterize in
detail by combining conductance and thermovoltage measurements with modeling.
Our results demonstrate that local polymer electrolyte gates are compatible
with nanowire thermoelectrics, where they offer the advantage of a very low
thermal conductivity, and hold great potential towards setting the optimal
operating point for solid-state cooling applications.Comment: Published in Advanced Functional Materials. Includes colour versions
of figures and supplementary informatio
Electrometry using the quantum Hall effect in a bilayer 2D electron system
We discuss the development of a sensitive electrometer that utilizes a
two-dimensional electron gas (2DEG) in the quantum Hall regime. As a
demonstration, we measure the evolution of the Landau levels in a second,
nearby 2DEG as the applied perpendicular magnetic field is changed, and extract
an effective mass for electrons in GaAs that agrees within experimental error
with previous measurements.Comment: 3.5 pages, 3 figures, submitted to APL
p-GaAs nanowire MESFETs with near-thermal limit gating
Difficulties in obtaining high-performance p-type transistors and gate
insulator charge-trapping effects present two major challenges for III-V
complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs
nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates
the need for a gate insulator by exploiting the Schottky barrier at the
metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire
metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical
sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio
, on-resistance ~700 k, contact resistance ~30 k,
peak transconductance 1.2 S/m and high-fidelity ac operation at
frequencies up to 10 kHz. The device consists of a GaAs nanowire with an
undoped core and heavily Be-doped shell. We carefully etch back the nanowire at
the gate locations to obtain Schottky-barrier insulated gates whilst leaving
the doped shell intact at the contacts to obtain low contact resistance. Our
device opens a path to all-GaAs nanowire MESFET complementary circuits with
simplified fabrication and improved performance
Using ultra-thin parylene films as an organic gate insulator in nanowire field-effect transistors
We report the development of nanowire field-effect transistors featuring an
ultra-thin parylene film as a polymer gate insulator. The room temperature,
gas-phase deposition of parylene is an attractive alternative to oxide
insulators prepared at high temperatures using atomic layer deposition. We
discuss our custom-built parylene deposition system, which is designed for
reliable and controlled deposition of <100 nm thick parylene films on III-V
nanowires standing vertically on a growth substrate or horizontally on a device
substrate. The former case gives conformally-coated nanowires, which we used to
produce functional -gate and gate-all-around structures. These give
sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding at
room temperature. For the gate-all-around structure, we developed a novel
fabrication strategy that overcomes some of the limitations with previous
lateral wrap-gate nanowire transistors. Finally, we show that parylene can be
deposited over chemically-treated nanowire surfaces; a feature generally not
possible with oxides produced by atomic layer deposition due to the surface
`self-cleaning' effect. Our results highlight the potential for parylene as an
alternative ultra-thin insulator in nanoscale electronic devices more broadly,
with potential applications extending into nanobioelectronics due to parylene's
well-established biocompatible properties
InAs nanowire transistors with multiple, independent wrap-gate segments
We report a method for making horizontal wrap-gate nanowire transistors with
up to four independently controllable wrap-gated segments. While the step up to
two independent wrap-gates requires a major change in fabrication methodology,
a key advantage to this new approach, and the horizontal orientation more
generally, is that achieving more than two wrap-gate segments then requires no
extra fabrication steps. This is in contrast to the vertical orientation, where
a significant subset of the fabrication steps needs to be repeated for each
additional gate. We show that cross-talk between adjacent wrap-gate segments is
negligible despite separations less than 200 nm. We also demonstrate the
ability to make multiple wrap-gate transistors on a single nanowire using the
exact same process. The excellent scalability potential of horizontal wrap-gate
nanowire transistors makes them highly favourable for the development of
advanced nanowire devices and possible integration with vertical wrap-gate
nanowire transistors in 3D nanowire network architectures.Comment: 18 pages, 5 figures, In press for Nano Letters (DOI below
Origin of the hysteresis in bilayer 2D systems in the quantum Hall regime
The hysteresis observed in the magnetoresistance of bilayer 2D systems in the
quantum Hall regime is generally attributed to the long time constant for
charge transfer between the 2D systems due to the very low conductivity of the
quantum Hall bulk states. We report electrometry measurements of a bilayer 2D
system that demonstrate that the hysteresis is instead due to non-equilibrium
induced current. This finding is consistent with magnetometry and electrometry
measurements of single 2D systems, and has important ramifications for
understanding hysteresis in bilayer 2D systems.Comment: 4 pages, 3 figs. Accepted for publication in PR
- …