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Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43014/1/10836_2004_Article_BF00972516.pd

Dirac electrons in the presence of matrix potential barrier: application to graphene and topological insulators

Scattering of a 2D Dirac electrons on a rectangular matrix potential barrier is considered using the formalism of spinor transfer matrices. It is shown, in particular, that in the absence of the mass term, the Klein tunneling is not necessarily suppressed but occurs at oblique incidence. The formalism is applied to studying waveguiding modes of the barrier, which are supported by the edge and bulk states. The condition of existence of the uni-directionality property is found. We show that the band of edge states is always finite with massless excitations, while the spectrum of the bulk states, depending on parameters of the barrier, may consist of the infinite or finite band with both, massive and massless, low-energy excitations. The effect of the Zeeman term is considered and the condition of appearance of two distinct energy dependent directions corresponding to the Klein tunneling is found.Comment: published versio

EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation

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Accurate estimating simultaneous switching noises by using application specific device modeling

Abstract In this paper, we study the simultaneous switching noise problem by using an application-specific modeling method.

A survey of DA techniques for PLD and FPGA based systems

Programmable logic devices (PLDs) are gaining in acceptance, of late, for designing systems of all complexities ranging from glue logic to special purpose parallel machines. Higher densities and integration levels are made possible by the new breed of complex PLDs and FPGAs. The added complexities of these devices make automatic computer aided tools indispensable for achieving good performance and a high usable gate-count. In this article, we attempt to present in an unified manner, the different tools and their underlying algorithms using an example of a vending machine controller as an illustrative example. Topics covered include logic synthesis for PLDs and FPGAs along with an in-depth survey of important technology mapping, partitioning and place and route algorithms for different FPGA architectures.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/31206/1/0000108.pd

A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices

An ultrafast 32-bit pipeline correlator has been implemented using resonant tunneling diodes (RTD) and hetero-junction bipolar transistors (HBT). The negative differential resistance (NDR) characteristics of RTD's is the basis of logic gates with the self-latching property that eliminates pipeline area and delay overheads which limit throughput in conventional technologies. The circuit topology also allows threshold logic functions such as minority/majority to be implemented in a compact manner resulting in reduction of the overall complexity and delay of arbitrary logic circuits. The parallel correlator is an essential component in code division multi-access (CDMA) transceivers used for the continuous calculation of correlation between an incoming data stream and a PN sequence. Simulation results show that a nano-pipelined correlator can provide and effective throughput of one 32-bit correlation every 100 picoseconds, using minimal hardware, with a power dissipation of 1.5 watts. RTD plus HBT based logic gates have been fabricated and the RTD plus HBT based correlator is compared with state of the art complementary metal oxide semiconductor (CMOS) implementations

Parallel Testing for Pattern Sensitive Faults in Semiconductor Random Access Memory

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / SRC RSCH 84-06-049-

Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome

The genetic algorithm has been applied to the VLSI module placement problem. This algorithm is an iterative, evolutional approach. A placement configutation is represented by a set of primitive features such as location and orientation, and the features are arranged in the form of a two-dimensional bitmap chromosome. The representation is flexible, and can handle arbitrarily shaped cells, and pads, and is applicable to the placement of macro cells, and gate arrays. Three new versions of genetic operators, namely, crossover, inversion and mutation, are used to explore the solution space. Crossover creates new configurations by combining attributes from a pair of existing configurations. This feature passing scheme constitutes the primary difference between our genetic approach and the other traditional searching techniques. Inversion enables more uniform inheritance of features from one generation to the next, and mutation prevents the algorithm from getting trapped at local optima. We have pointed out that the bitmap representation enables the algorithm to divide the entire solution space into a set of feature-equivalent classes, or schemata where each class contains a set of solutions with common physical attributes. We show that the genetic algorithm adaptively biases the search based on the past observed fitness of the schemata. We also demonstrated the power of the genetic algorithm experimentally for macro cell placement, and obtained satisfactory results.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/29041/1/0000074.pd