Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities

none 39 The SLIM5 collaboration has designed, fabricated and tested several prototypes of CMOS Monolithic Active Pixel Sensors (MAPS). The key feature of these devices, with respect to traditional MAPS is to include, at the pixel level, charge amplification and shaping and a first sparsification structure that interfaces with on-chip digital readout circuits. Via the 3-well option of the applied View the MathML source ST-Microelectronics CMOS technology each pixel includes a charge preamplifier, a shaper, a discriminator, an output latch, while retaining a fill factor of the sensitive area close to 90%. The last device of the family was submitted on Q4 2006 and the tests are ongoing. On this sensor, an on-chip, off-pixel digital readout block (streamout data sparsification) was added to implement, to control and to readout a test matrix built up of 4×4 pixels. It is aimed at proposing solutions that will overcome the readout speed limit of future large-matrix MAPS chips. http://dx.doi.org/10.1016/j.nima.2007.07.135 none G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vitale G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vital

CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging

A 3D, through silicon via microelectronic process, capable of face-to-face assembling two 130 nm CMOS tiers in a single bi-layer wafer, has been exploited for the design of monolithic active pixels (MAPS), featuring a deep N-well (DNW) collecting electrode. They are expected to improve on planar CMOS DNW MAPS in terms of charge collection efficiency since most of the PMOS transistors in the front-end electronics, with their N-wells, can be moved to a different layer from that of the DNW sensor. The vertical integration process also requires that one of the two CMOS tiers be thinned down to a mere 6 m to expose the through silicon vias and contact the sandwiched circuits. In this work, results from device simulations of 3D MAPS will be presented. The aim is to evaluate the potential of such a thin sensitive substrate in the detection of low energy particles (in the tens of keV range), in view of possible applications to biomedical imaging

PixFEL: development of an X-ray diffraction imager for future FEL applications

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA output is processed by a time-variant shaper performing gated integration and correlated double sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel cameras at FELs) imager

Large-area Si(Li) Detectors for X-ray Spectrometry and Particle Tracking for the GAPS Experiment

Large-area lithium-drifted silicon (Si(Li)) detectors, operable 150{\deg}C above liquid nitrogen temperature, have been developed for the General Antiparticle Spectrometer (GAPS) balloon mission and will form the first such system to operate in space. These 10 cm-diameter, 2.5 mm-thick multi-strip detectors have been verified in the lab to provide <4 keV FWHM energy resolution for X-rays as well as tracking capability for charged particles, while operating in conditions (~-40{\deg}C and ~1 Pa) achievable on a long-duration balloon mission with a large detector payload. These characteristics enable the GAPS silicon tracker system to identify cosmic antinuclei via a novel technique based on exotic atom formation, de-excitation, and annihilation. Production and large-scale calibration of ~1000 detectors has begun for the first GAPS flight, scheduled for late 2021. The detectors developed for GAPS may also have other applications, for example in heavy nuclei identification

Comments by the Senior Editor

n/

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: Experimental Results

This work is concerned with the experimental characterization of a Charge Sensitive Amplifier featuring dynamic signal compression, fast recovery time, low noise and reduced area occupancy. The device takes advantage of the non-linear characteristic of a feedback transistor which behaves like a voltage controlled capacitance. This property has been exploited to fit a wide input dynamic range into the available output swing. The charge amplifier can be operated in synchronous mode at high frame rates, of the order of few MHz, thanks to a wide bandwidth, an improved output stage and a fast reset network. Thanks to the small area occupancy the amplifier is suitable for integration in a 100×100 μm2 pixel area. All these features make the device a good candidate for applications where a fast frontend with a non-linear response is required, such as in imaging instrumentation for Free Electron Laser experiments. The aim of the paper is to present and discuss the experimental results coming from the characterization of the first prototype of the circuit which has been designed in a 65 nm CMOS technology. The work has been carried out in the frame of the PixFEL Project funded by the INFN, Italy

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range