Comparison of Adaptive Control Architectures for Flutter Suppression

A study is conducted to derive and implement a state feedback model reference adaptive control (MRAC) solutions for a 2-D aeroelastic nonlinear system and in evaluating the robustness of different control strategies to damage leading to the deterioration of the structural stiffness characteristics. The standard MRAC, a modified MRAC and the adaptive controller are the three model reference adaptive control solutions analyzed. The standard direct MRAC solution serves as the threshold to assess whether or not the more complex algorithms are an effective improvement to it

Measurements and tests on FBK silicon sensors with an optimized electronic design for a CTA camera

In October 2013, the Italian Ministry approved the funding of a Research & Development (R&D) study, within the "Progetto Premiale TElescopi CHErenkov made in Italy (TECHE)", devoted to the development of a demonstrator for a camera for the Cherenkov Telescope Array (CTA) consortium. The demonstrator consists of a sensor plane based on the Silicon Photomultiplier (SiPM) technology and on an electronics designed for signal sampling. Preliminary tests on a matrix of sensors produced by the Fondazione Bruno Kessler (FBK-Trento, Italy) and on electronic prototypes produced by SITAEL S.p.A. will be presented. In particular, we used different designs of the electronics in order to optimize the output signals in terms of tail cancellation. This is crucial for applications where a high background is expected, as for the CTA experiment.Comment: 5 pages, 6 figures; Proceedings of the 10th Workshop on Science with the New Generation of High-Energy Gamma-ray experiments (SciNeGHE) - PoS(Scineghe2014)00

UFT/leucovorin and oxaliplatin alternated with UFT/leucovorin and irinotecan in metastatic colorectal cancer

A total of 41 metastatic colorectal cancer (CRC) patients received tegafur/uracil (UFT)+leucovorin (LV)+oxaliplatin alternated with UFT/LV+irinotecan. The overall response rate was 58.5% (95% confidence interval, 42.2-73.3%), and the median progression-free survival was 8.8 months. There were no grade 4 toxicities; 12 patients (29%) experienced grade 3 diarrhoea. There were no cases of hand-foot syndrome. This alternating regimen seems to be effective and well tolerated in the first-line treatment of patients with metastatic CRC

Higgs Low-Energy Theorem (and its corrections) in Composite Models

The Higgs low-energy theorem gives a simple and elegant way to estimate the couplings of the Higgs boson to massless gluons and photons induced by loops of heavy particles. We extend this theorem to take into account possible nonlinear Higgs interactions resulting from a strong dynamics at the origin of the breaking of the electroweak symmetry. We show that, while it approximates with an accuracy of order a few percents single Higgs production, it receives corrections of order 50% for double Higgs production. A full one-loop computation of the gg->hh cross section is explicitly performed in MCHM5, the minimal composite Higgs model based on the SO(5)/SO(4) coset with the Standard Model fermions embedded into the fundamental representation of SO(5). In particular we take into account the contributions of all fermionic resonances, which give sizeable (negative) corrections to the result obtained considering only the Higgs nonlinearities. Constraints from electroweak precision and flavor data on the top partners are analyzed in detail, as well as direct searches at the LHC for these new fermions called to play a crucial role in the electroweak symmetry breaking dynamics.Comment: 30 pages + appendices and references, 12 figures. v2: discussion of flavor constraints improved; references added; electroweak fit updated, results unchanged. Matches published versio

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Generalised geometrical CP violation in a T' lepton flavour model

We analyse the interplay of generalised CP transformations and the non-Abelian discrete group T \u2032 and use the semi-direct product G f = T \u2032 caH CP, as family symmetry acting in the lepton sector. The family symmetry is shown to be spontaneously broken in a geometrical manner. In the resulting flavour model, naturally small Majorana neutrino masses for the light active neutrinos are obtained through the type I see-saw mechanism. The known masses of the charged leptons, lepton mixing angles and the two neutrino mass squared differences are reproduced by the model with a good accuracy. The model allows for two neutrino mass spectra with normal ordering (NO) and one with inverted ordering (IO). For each of the three spectra the absolute scale of neutrino masses is predicted with relatively small uncertainty. The value of the Dirac CP violation (CPV) phase \u3b4 in the lepton mixing matrix is predicted to be \u3b4 = \u3c0/2 or 3\u3c0/2. Thus, the CP violating effects in neutrino oscillations are predicted to be maximal (given the values of the neutrino mixing angles) and experimentally observable. We present also predictions for the sum of the neutrino masses, for the Majorana CPV phases and for the effective Majorana mass in neutrinoless double beta decay. The predictions of the model can be tested in a variety of ongoing and future planned neutrino experiments

Renormalisation group corrections to neutrino mixing sum rules

Neutrino mixing sum rules are common to a large class of models based on the (discrete) symmetry approach to lepton flavour. In this approach the neutrino mixing matrix $U$ is assumed to have an underlying approximate symmetry form \tildeU_\nu, which is dictated by, or associated with, the employed (discrete) symmetry. In such a setup the cosine of the Dirac CP-violating phase $\delta$ can be related to the three neutrino mixing angles in terms of a sum rule which depends on the symmetry form of \tildeU_\nu. We consider five extensively discussed possible symmetry forms of \tildeU_\nu: i) bimaximal (BM) and ii) tri-bimaximal (TBM) forms, the forms corresponding to iii) golden ratio type A (GRA) mixing, iv) golden ratio type B (GRB) mixing, and v) hexagonal (HG) mixing. For each of these forms we investigate the renormalisation group corrections to the sum rule predictions for $\delta$ in the cases of neutrino Majorana mass term generated by the Weinberg (dimension 5) operator added to i) the Standard Model, and ii) the minimal SUSY extension of the Standard Model

Combined explanations of B-physics anomalies: the sterile neutrino solution

In this paper we provide a combined explanation of charged- and neutral-current B-physics anomalies assuming the presence of a light sterile neutrino NR which contributes to the B \u2192 D(*)\u3c4\u3bd processes. We focus in particular on two simplified models, where the mediator of the flavour anomalies is either a vector leptoquark U1\u3bc 3c (3, 1, 2/3) or a scalar leptoquark S1 3c (3\uaf , 1, 1/3). We find that U1\u3bc can successfully reproduce the required deviations from the Standard Model while being at the same time compatible with all other flavour and precision observables. The scalar leptoquark instead induces a tension between Bs mixing and the neutral-current anomalies. For both states we present the limits and future projections from direct searches at the LHC finding that, while at present both models are perfectly allowed, all the parameter space will be tested with more luminosity. Finally, we study in detail the cosmological constraints on the sterile neutrino NR and the conditions under which it can be a candidate for dark matter

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started