Numerical Simulation of Transient Response in 3-D Multi-Channel Nanowire MOSFETs Submitted to Heavy Ion Irradiation

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Contact resistances in trigate and FinFET devices in a Non-Equilibrium Green's Functions approach

We compute the contact resistances $R_{\rm c}$ in trigate and FinFET devices with widths and heights in the 4 to 24 nm range using a Non-Equilibrium Green's Functions approach. Electron-phonon, surface roughness and Coulomb scattering are taken into account. We show that $R_{\rm c}$ represents a significant part of the total resistance of devices with sub-30 nm gate lengths. The analysis of the quasi-Fermi level profile reveals that the spacers between the heavily doped source/drain and the gate are major contributors to the contact resistance. The conductance is indeed limited by the poor electrostatic control over the carrier density under the spacers. We then disentangle the ballistic and diffusive components of $R_{\rm c}$, and analyze the impact of different design parameters (cross section and doping profile in the contacts) on the electrical performances of the devices. The contact resistance and variability rapidly increase when the cross sectional area of the channel goes below $\simeq 50$ nm$^2$. We also highlight the role of the charges trapped at the interface between silicon and the spacer material.Comment: 16 pages, 15 figure

Nanowires: Promising Candidates for Electrostatic Control in Future Nanoelectronic Devices

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Modélisation du transport quasi-balistique pour la simulation de circuits à base de nano-transistor multigrilles.

Today, the MOSFET transistor reaches decananometer dimensions for which the effects of ballistic transport can no longer be neglected. The challenge is therefore to be able to introduce (quasi-)ballistic transport in the modeling of new devices and evaluates its impact at the circuit level. In this context, our work focuses on the introduction of (quasi-)ballistic transport in compact model of multigate transistor for the simulation of circuit elements. Firstly, the McKelvey's method applied to MOSFET has been used to synthesize all existing works on analytical modeling of ballistic/quasi-ballistic transport. Then, we built a macroscopic model called "quasi-ballistic mobility" (starting from pioneering work of Rhew et al), following the comparison between the moment method and the McKelvey method to describe (quasi-)ballistic transport in TCAD environment. Secondly, results from this first model have led us to build our (quasi-)ballistic current by adapting or creating new approaches to take into account the various effects of nanoscale devices: the short-channel effects, the quantum confinement and scattering rate. Finally, our work investigates the impact of the transport properties on the performances of circuit operation.Le transistor MOSFET atteint aujourd'hui des dimensions déca nanométriques pour lesquelles les effets de balisticité ne peuvent plus être négligés. Le challenge actuel est d'être capable d'introduire le transport (quasi-)balistique dans la modélisation des dispositifs innovants et d'évaluer son impact au niveau système. Dans ce contexte, notre travail porte sur l'introduction du transport (quasi-)balistique dans une modélisation analytique des transistors MOS multigrilles pour la simulation d'éléments de circuit. Dans un premier temps, la redécouverte de la méthode de McKelvey appliquée au transistor MOSFET a permis de synthétiser l'ensemble des travaux concernant la modélisation analytique du transport balistique/quasi-balistique. Nous avons alors construit une modélisation appelée « mobilité quasi-balistique » (à partir des travaux de Rhew et al), issue du rapprochement entre la méthode des moments et la méthode de McKelvey permettant de décrire le transport (quasi-)balistique de façon macroscopique dans un environnement TCAD. L'ensemble des résultats issus de cette première modélisation nous a dirigé dans la construction de notre modèle analytique de courant (quasi-)balistique en adaptant ou en créant de nouvelles approches pour prendre en compte les divers effets des dispositifs nanométriques : les effets de canal court, le confinement quantique et la description des interactions. Nous avons donc pu quantifier l'impact des propriétés de transport électronique sur le fonctionnement d'éléments de circuit et cela en fonction du type d'architecture

Physics-Based Analytical Modeling of Quasi-Ballistic Transport in Double-Gate MOSFETs: From Device to Circuit Operation

International audienceWe developed an original physics-based unified analytical model describing the transport from diffusive to ballistic regimes in double-gate MOSFETs. This model includes a new analytical model of the backscattering coefficient based on an accurate empirical approach. In addition, short-channel effects, carrier quantum-mechanical confinement, and degeneracy are considered. For the first time, we used the model to analyze and quantify the real impact of ballistic/quasi-ballistic transport on circuit performances. We show how the switching times of CMOS inverters and the oscillation frequencies of ring oscillators are improved when considering ballistic instead of diffusive transport. Finally, our model is fully validated at both device and circuit levels using numerical simulation and experimental data

Underground characterization and modeling of alpha-particle induced Soft-Error Rate in CMOS 65nm SRAM

International audienceThis work reports a long-duration (~ 3 years) real-time underground experiment of 65 nm SRAM technology at the underground laboratory of Modane (LSM) to quantify the impact of alpha-emitter on Soft Error Rate. We developed an original and full analytical charge deposition based on non constant Linear Energy Transfer (LET) to accurately model the diffusion/collection approach. Monte-Carlo simulation results based on this new model have been confronted to experimental data to analyze the alpha-particles impact on Multiple Ship Upset

Single Event Transient Compact Model for FDSOI MOSFETs Taking Bipolar Amplification and Circuit Level Arbitrary Generation Into Account

International audienceSingle Event Transients (SET) are ionizing particles induced current pulses which are able to generate soft errors in CMOS circuits. In Silicon-on-Insulator (SOI) technologies, bipolar amplification phenomena is more significant due to presence of the Burried Oxide (BOX), which is detrimental to soft errors sensitivity. State of the art FDSOI SET models account for bipolar amplification through a dynamic pre-factor. This approach is mainly empirical and not compact. In this work, we propose a SET compact model for FDSOI MOSFETs including a physical modeling of bipolar amplification. Results are validated through TCAD simulations. A circuit level approach is proposed considering arbitrary generation within functional SRAM cell. This approach allows more realistic Single Event Upset (SEU) prediction and we show how circuit level generation can influence SEU prediction

Analytical Modeling of Alpha-Particle Emission Rate at Wafer-Level

IEEE Radiation Effects Data Workshop (REDW)/48th IEEE International Nuclear and Space Radiation Effects Conference (NSREC), Las Vegas, NV, JUL 25-29, 2011International audienceAlpha-particle emissivity at wafer-level has been analytically modeled for material layers contaminated by uranium and/or thorium impurities. Our approach evaluates the number (or the fraction) of escaping alpha particles from any monolayer or multilayer of arbitrary material composition. The global emissivity of the (stacked) material and its corresponding alpha-particle energy spectrum can be also analytically derived. The model has been fully validated with Monte Carlo simulation in terms of alpha-particle emissivity and energy spectra for different layer thicknesses and detection threshold energies. Finally, we propose a general nomogram for silicon material directly giving the alpha-particle emissivity versus the silicon contamination level expressed in ppb of uranium and thorium

Numerical simulation of quasi-ballistic transport in fully-depleted SOI and double-gate MOSFETs: application to the analysis of circuit performances

International audienc