246 research outputs found
Reconfiguration Viewer
Grassi PR, Pohl C, Porrmann M. Reconfiguration Viewer. In: Design Automation and Test in Europe, DATE University Booth. Nice, France; 2009.The proposed approach allows debugging of partial dynamic reconfiguration. It shows where and when FPGA areas are reconfigured at runtime
A reconfigurable ethernet switch for self-optimizing communication systems
Self-optimization is a promising approach to cope with the increasing complexity of today’s automation networks. The high complexity is mainly caused by a rising amount of network nodes and increasing real-time requirements. Dynamic hardware reconfiguration is a key technology for self-optimizing systems, enabling, e.g., Real-Time Communication Systems (RCOS) that adapt to varying requirements at runtime. Concerning dynamic reconfiguration of an RCOS, an important requirement is to maintain connections and to support time-constrained communication during reconfigu-ration. We have developed a dynamically reconfigurable Ethernet switch, which is the main building block of a prototypic implementation of an RCOS network node. Three methods for reconfiguring the Ethernet switch without packet loss are presented. A prototypical implementation of one method is described and analyzed in respect to performance and resource efficiency.1st IFIP International Conference on Biologically Inspired Cooperative Computing - CommunicationRed de Universidades con Carreras en Informática (RedUNCI
Towards 6D MCL for LiDARs in 3D TSDF Maps on Embedded Systems with GPUs
Monte Carlo Localization is a widely used approach in the field of mobile
robotics. While this problem has been well studied in the 2D case, global
localization in 3D maps with six degrees of freedom has so far been too
computationally demanding. Hence, no mobile robot system has yet been presented
in literature that is able to solve it in real-time. The computationally most
intensive step is the evaluation of the sensor model, but it also offers high
parallelization potential. This work investigates the massive parallelization
of the evaluation of particles in truncated signed distance fields for
three-dimensional laser scanners on embedded GPUs. The implementation on the
GPU is 30 times as fast and more than 50 times more energy efficient compared
to a CPU implementation
The Comprehensive MAC Taxonomy Database: comatose
Braun LD, Porrmann M. The Comprehensive MAC Taxonomy Database: comatose.; 2018.The comprehensive MAC taxonomy database (comatose) is a collection of 327 wireless media/medium access protocols published between 1970 and 2017. The latest version is available [online](https://6xq.net/comatose/)
Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs
Kaiser M, Pilz S, Porrmann F, Hagemeyer J, Porrmann M. Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. In: 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book. Vol 12. Bielefeld; 2018: 48-49
Survey of FPGA applications in the period 2000 – 2015 (Technical Report)
Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs
Compiler-Driven Reconfiguration of Multiprocessors
Hussmann M, Thies M, Kastens U, Purnaprajna M, Porrmann M, Rückert U. Compiler-Driven Reconfiguration of Multiprocessors. In: Proceedings of the Workshop on Application Specific Processors (WASP) 2007. 2007.Multiprocessors enable parallel execution of a single large
application to achieve a performance improvement. An application
is split at instruction, data or task level (based on
the granularity), such that the overhead of partitioning is
minimal. Parallelization for multiprocessors is mostly restricted
to a fixed granularity. Reconfiguration enables architectural
variations to allow multiple granularities of operation
within a multiprocessor. This adaptability optimizes
resource utilization over a fixed organization.
Here, a unified hardware-software approach to design a
reconfigurable multiprocessor system called QuadroCore is
presented. In our holistic methodology, compiler-driven reconfiguration
selects from a fixed set of modes. Each mode
relies on matching program analysis to exploit the architecture
efficiently. For instance, a multiprocessor may adapt
to different parallelization paradigms. The compiler can
determine the best execution mode for each piece of code
by analyzing the parallelism in a program. A fast, singlecycle,
run-time reconfiguration between these predetermined
modes is enabled by executing special instructions which
switch coarse-grained components like instruction decoders,
ALUs and register banks. Performance is evaluated in terms
of execution cycles and achieved clock frequency. First results
indicate suitability especially in audio and video processing
applications
Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems
This paper introduces a methodology to develop energy models for the design
space exploration of embedded many-core systems. The design process of such
systems can benefit from sophisticated models. Software and hardware can be
specifically optimized based on comprehensive knowledge about application
scenario and hardware behavior. The contribution of our work is an automated
framework to estimate the energy consumption at an arbitrary abstraction level
without the need to provide further information about the system. We validated
our framework with the configurable many-core system CoreVA-MPSoC. Compared to
a simulation of the CoreVA-MPSoC on gate level in a 28nm FD-SOI standard cell
technology, our framework shows an average estimation error of about 4%.Comment: Presented at HIP3ES, 201
A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing
Kaiser M, Griessl R, Hagemeyer J, et al. A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. In: Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17). Denver, CO; 2017
OLT(RE)2: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems
Reconfigurable systems gained great interest in a wide range of application fields, including aerospace, where electronic devices are exposed to a very harsh working environment. Commercial SRAM-based FPGA devices represent an extremely interesting hardware platform for this kind of systems since they combine low cost with the possibility to utilize state-of-the-art processing power as well as the flexibility of reconfigurable hardware. In this paper we present OLT(RE)2: an on-line on-demand approach to test permanent faults induced by radiation in reconfigurable systems used in space missions. The proposed approach relies on a test circuit and on custom place-and-route algorithms. OLT(RE)2 exploits partial dynamic reconfigurability offered by today’s SRAM-based FPGAs to place the test circuits at run-time. The goal of OLT(RE)2 is to test unprogrammed areas of the FPGA before using them, thus preventing functional modules of the reconfigurable system to be placed on areas with faulty resources. Experimental results have shown that (i) it is possible to generate, place and route the test circuits needed to detect on average more than 99 % of the physical wires and on average about 97 % of the programmable interconnection points of an arbitrary large region of the FPGA in a reasonable time and that (ii) it is possible to download and run the whole test suite on the target device without interfering with the normal functioning of the system
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