FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video

Circuits and systems able to process high quality video in real time are fundamental in nowadays imaging systems. The circuit proposed in the paper, aimed at the robust identification of the background in video streams, implements the improved formulation of the Gaussian Mixture Model (GMM) algorithm that is included in the OpenCV library. An innovative, hardware oriented, formulation of the GMM equations, the use of truncated binary multipliers, and ROM compression techniques allow reduced hardware complexity and increased processing capability. The proposed circuit has been designed having commercial FPGA devices as target and provides speed and logic resources occupation that overcome previously proposed implementations. The circuit, when implemented on Virtex6 or StratixIV, processes more than 45 frame per second in 1080p format and uses few percent of FPGA logic resources

BHPR research: qualitative1. Complex reasoning determines patients' perception of outcome following foot surgery in rheumatoid arhtritis

Background: Foot surgery is common in patients with RA but research into surgical outcomes is limited and conceptually flawed as current outcome measures lack face validity: to date no one has asked patients what is important to them. This study aimed to determine which factors are important to patients when evaluating the success of foot surgery in RA Methods: Semi structured interviews of RA patients who had undergone foot surgery were conducted and transcribed verbatim. Thematic analysis of interviews was conducted to explore issues that were important to patients. Results: 11 RA patients (9 ♂, mean age 59, dis dur = 22yrs, mean of 3 yrs post op) with mixed experiences of foot surgery were interviewed. Patients interpreted outcome in respect to a multitude of factors, frequently positive change in one aspect contrasted with negative opinions about another. Overall, four major themes emerged. Function: Functional ability & participation in valued activities were very important to patients. Walking ability was a key concern but patients interpreted levels of activity in light of other aspects of their disease, reflecting on change in functional ability more than overall level. Positive feelings of improved mobility were often moderated by negative self perception ("I mean, I still walk like a waddling duck”). Appearance: Appearance was important to almost all patients but perhaps the most complex theme of all. Physical appearance, foot shape, and footwear were closely interlinked, yet patients saw these as distinct separate concepts. Patients need to legitimize these feelings was clear and they frequently entered into a defensive repertoire ("it's not cosmetic surgery; it's something that's more important than that, you know?”). Clinician opinion: Surgeons' post operative evaluation of the procedure was very influential. The impact of this appraisal continued to affect patients' lasting impression irrespective of how the outcome compared to their initial goals ("when he'd done it ... he said that hasn't worked as good as he'd wanted to ... but the pain has gone”). Pain: Whilst pain was important to almost all patients, it appeared to be less important than the other themes. Pain was predominately raised when it influenced other themes, such as function; many still felt the need to legitimize their foot pain in order for health professionals to take it seriously ("in the end I went to my GP because it had happened a few times and I went to an orthopaedic surgeon who was quite dismissive of it, it was like what are you complaining about”). Conclusions: Patients interpret the outcome of foot surgery using a multitude of interrelated factors, particularly functional ability, appearance and surgeons' appraisal of the procedure. While pain was often noted, this appeared less important than other factors in the overall outcome of the surgery. Future research into foot surgery should incorporate the complexity of how patients determine their outcome Disclosure statement: All authors have declared no conflicts of interes

Hardware architectures for real time processing of High Definition video sequences

Actually, application fields, such as medicine, space exploration, surveillance, authentication, HDTV, and automated industry inspection, require capturing, storing and processing continuous streams of video data. Consequently, different process techniques (video enhancement, segmentation, object detection, or video compression, as examples) are involved in these applications. Such techniques often require a significant number of operations depending on the algorithm complexity and the video resolution, which make impossible a time efficient software implementation. The actual demand, driven by the consumer electronics market, of lightweight and high performance portable systems capable of processing high definition (HD) video sequences in real-time is therefore mainly targeted through the use of integrated digital electronic systems. Very high performance can be obtained by using full custom ASIC implementations. However, the complexity and the cost associated with ASIC design is significant. Moreover, ASIC implementations are not reconfigurable and require a long design time. For these reasons, Field Programmable Gate Array (FPGA) devices are more and more being chosen as target technology for the hardware acceleration. In this dissertation, several hardware architectures for real-time video processing of HD video sequences are proposed. The circuits are designed by using Hardware Description Languages (HDL) and the target technologies for the implementation are mainly FPGA devices. Area utilization, maximum working frequency, and power dissipation are also computed and analyzed for all the described architectures and several experiments are carried out to test the circuits characteristics. The comparison with previously proposed works shows that circuits performance overcome the state-of-the-art architectures, highlighting the effectiveness of the proposed solutions

Direct Digital Frequency Synthesizers implemented on high end FPGA devices

Direct Digital Frequency Synthesizer (DDFS) circuits are routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed and optimized for ASIC (Application Specific Integrated Circuits) implementations. Nowadays, FPGA devices are frequently chosen as target for digital circuits. This paper presents the FPGA implementation of state of the art DDFS architectures and compares their performance providing hints on optimal design as a function of the chosen performance parameter

ASIC and FPGA implementation of the Gaussian Mixture Model algorithm for real-time segmentation of High Definition video

Background identification is a common feature in many video processing systems. The paper proposes two hardware implementations of the OpenCV version of the Gaussian Mixture Model (GMM), a background identification algorithm. The implemented version of the algorithm allows a fast initialization of the background model while an innovative, hardware oriented, formulation of the GMM equations makes the proposed circuits able to perform real time background identification on High Definition (HD) video sequences with frame size 19201080. The first of the two circuits has been designed having commercial FPGA devices as target. When implemented on Virtex6 vlx75t, the proposed circuit processes 91 HD fps and uses 3% of FPGA logic resources. The second circuit has been oriented to the implementation in UMC-90nm CMOS standard cell technology and is proposed in two versions. Both versions can process at a frame rate higher than 60 HD fps. The first version uses the constant voltage scaling technique to provide a low power implementation. It provides silicon area occupation of 28847 m2 and energy dissipation per pixel of 15.3 pJ/pixel. The second version is designed to reduce silicon area utilization and occupies 21847 m2 with an energy dissipation of 49.4 pJ/pixel

Processor core for real time background identification of HD video based on OpenCV Gaussian mixture model algorithm

The identification of moving objects is a fundamental step in computer vision processing chains. The development of low cost and lightweight smart cameras steadily increases the request of efficient and high performance circuits able to process high definition video in real time. The paper proposes two processor cores aimed to perform the real time background identification on High Definition (HD, 1920 1080 pixel) video streams. The implemented algorithm is the OpenCV version of the Gaussian Mixture Model (GMM), an high performance probabilistic algorithm for the segmentation of the background that is however computationally intensive and impossible to implement on general purpose CPU with the constraint of real time processing. In the proposed paper, the equations of the OpenCV GMM algorithm are optimized in such a way that a lightweight and low power implementation of the algorithm is obtained. The reported performances are also the result of the use of state of the art truncated binary multipliers and ROM compression techniques for the implementation of the non-linear functions. The first circuit has commercial FPGA devices as a target and provides speed and logic resource occupation that overcome previously proposed implementations. The second circuit is oriented to an ASIC (UMC-90nm) standard cell implementation. Both implementations are able to process more than 60 frames per second in 1080p format, a frame rate compatible with HD television

FPGA-based architecture for real time segmentation and denoising of HD video

The identification of moving objects is a basic step in computer vision. The identification begins with the segmentation and is followed by a denoising phase. This paper proposes the FPGA hardware implementation of segmentation and denoising unit. The segmentation is conducted using the Gaussian mixture model (GMM), a probabilistic method for the segmentation of the background. The denoising is conducted implementing the morphological operators of erosion, dilation, opening and closing. The proposed circuit is optimized to perform real time processing of HD video sequences (1,920 9 1,080 @ 20 fps) when implemented on FPGA devices. The circuit uses an optimized fixed width representation of the data and implements high performance arithmetic circuits. The circuit is implemented on Xilinx and Altera FPGA. Implemented on xc5vlx50 Virtex5 FPGA, it can process 24 fps of an HD video using 1,179 Slice LUTs and 291 Slice Registers; the dynamic power dissipation is 0.46 mW/MHz. Implemented on EP2S15F484C3 StratixII, it provides a maximum working frequency of 44.03 MHz employing 5038 Logic Elements and 7,957 flip flop with a dynamic power dissipation of 4.03 mW/MHz

State of the art direct digital frequency synthesis methodologies and their performance on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed but they optimize the performance for a given ASIC (Application Specific Integrated Circuits) technology. Nowadays, FPGA are very often used for the release of electronic systems. As a consequence, the study of the performance of advanced DDFS design techniques when implemented on FPGA devices, is of great interest. The paper presents various implementation of state of the art DDFS on various FPGA and compares their performance providing hints on optimal design as a function of the chosen performance parameter

FPGA implementation of OpenCV compatible background identification circuit

The paper proposes the hardware implementation of the Gaussian Mixture Model (GMM) algorithm included in the OpenCV library. The OpenCV GMM algorithm is adapted to allow the FPGA implementation while providing a minimal impact on the quality of the processed videos. The circuit performs 30 frame per second (fps) background (Bg) identification on High Definition (HD) video sequences when implemented on commercial FPGA and outperforms previously proposed implementations. When implemented on Virtex5 lx50 FPGA using one level of pipeline, runs at 95.3 MHz, uses 5.3% of FPGA resources with a power dissipation of 1.47 mW/MHz