Contribution of unexplored genomic variations to neurodevelopmental disorders

Neurodevelopmental disorders are a group of conditions with impairments of the personal, social, academic or occupational behaviour. Autism spectrum disorder is a neurodevelopmental disorder with a high genetic component with a large fraction still unknown. In this dissertation we analyse two unexplored genomic variants: Chromosomal mosaicism and Ancestral polymorphic inversions. Chromosomal mosaic events are responsible for a small but significant proportion of patients with ASD (0.45%), with the additional detection of two loss of chromosome Y events. In addition, we developed a bioinformatic tool that improves previous methods to detect loss of chromosome Y: MADloy. In the study of ancestral polymorphic inversions, inv8p23.1 and inv17q21.31 inversions were associated with autism risk. Improvements on the method to genotype ancestral polymorphic inversions allowed the prediction of a novel inversion in 22q11.21 region which has been validated by fiber-FISH.Els trastorns del neurodesenvolupament son un grup de condicions amb discapacitats conductuals en els àmbits personals, socials, acadèmics o ocupacionals. Els trastorns d’espectre autista són un trastorn del neurodesenvolupament amb una gran component genètica, part de la qual encara es desconeguda. En aquest treball analitzem dues variants genòmiques poc explorades: els reordenaments cromosòmics en mosaic I les inversions ancestrals polimòrfiques. Els reordenaments cromosòmics en Mosaic son responsables d’una significant però petita proporció dels pacients amb trastorn d’espectre autista (0.45%), amb la detecció addicional de dues pèrdues del cromosoma Y. Addicionalment, s’ha desenvolupat una eina bioinformàtica que millora els mètodes previs per detectar la pèrdua de cromosoma Y: MADloy. En l’estudi de les inversions ancestrals polimòrfiques, les inversions inv8p23.1 i inv17q21.31 s’han associat amb el risc d’autisme. Millores en el mètode de genotipació de les inversions ha permès la predicció de una nova inversió localitzada a la regió 22q11.21 que s’ha validat per fiber-FISH

Design of an Efficient Interconnection Network of Temperature Sensors

Temperature has become a first class design constraint because high temperatures adversely affect circuit reliability, static power and degrade the performance. In this scenario, thermal characterization of ICs and on-chip temperature monitoring represent fundamental tasks in electronic design. In this work, we analyze the features that an interconnection network of temperature sensors must fulfill. Departing from the network topology, we continue with the proposal of a very light-weight network architecture based on digitalization resource sharing. Our proposal supposes a 16% improvement in area and power consumption compared to traditional approache

Analysis of relod.net, a basic implementation of the RELOAD protocol for peer-to-peer networks

Actas de: XI Jornadas de Ingeniería Telemática (JITEL 2013) celebradas en Granada, 28-30 Octubre 2013. La web del evento es: http://dtstc.ugr.es/jitel2013/#The P2PSIP Working Group is chartered to develop protocols and mechanisms for the use of SIP in distributed environments, thus minimizing the need for centralized servers. Under this premise, the RELOAD protocol was created, whose design was generalized to accept other applications with similar requirements, and which is currently in process of standardization by the IETF. In this paper, we present a basic implementation and an analysis of this protocol proposed standard, given the great interest displayed in recent years by the scientific and business community in issues related to peerto- peer networks. Later, we conduct several experiments in order to validate its correct operation in real scenarios and provide feedback in relation with the current specificationThis research was supported in part by the Comunidad de Madrid grant S-2009/TIC-1468 (MEDIANET project).Publicad

Preparation and Characterization of New Liposomes. Bactericidal Activity of Cefepime Encapsulated into Cationic Liposomes

Cefepime is an antibiotic with a broad spectrum of antimicrobial activity. However, this antibiotic has several side effects and a high degradation rate. For this reason, the preparation and characterization of new liposomes that are able to encapsulate this antibiotic seem to be an important research line in the pharmaceutical industry. Anionic and cationic liposomes were prepared and characterized. All cationic structures contained the same cationic surfactant, N,N,N-triethyl-N-(12-naphthoxydodecyl)ammonium. Results showed a better encapsulation-efficiency percentage (EE%) of cefepime in liposomes with phosphatidylcholine and cholesterol than with 1,2-dioleoyl-sn-glycero-3-phosphoethanolamine (DOPE). The presence of cholesterol and the quantity of egg-yolk phospholipid in the liposome increased the encapsulation percentage. The bactericidal activity against Escherichia coli of cefepime loaded into liposomes with phosphatidylcholine was measured. The inhibitory zone in an agar plate for free cefepime was similar to that obtained for loaded cefepime. The growth-rate constant of E. coli culture was also measured in working conditions. The liposome without any antibiotic exerted no influence in such a rate constant. All obtained results suggest that PC:CH:12NBr liposomes are biocompatible nanocarriers of cefepime that can be used in bacterial infections against Escherichia coli with high inhibitory activity

Senior Games

Nuestro proyecto pretende prestar atención a un grupo de personas que no siempre recibe toda la que necesita. Estas son las personas mayores, las cuales sufren un declive cognitivo debido al envejecimiento. Debido a esto, hemos desarrollado un videojuego serio que servirá para estudiar y analizar (GA) las capacidades de las personas mayores, como: memoria, orientación, atención, planificación o percepción. No pretendemos que el videojuego resuelva ni mejore los deterioros o problemas que presenten los jugadores por sí mismo. La función del videojuego es recoger, de manera entretenida y a la vez rigurosa, datos sobre el comportamiento de nuestros jugadores frente a situaciones típicas de la vida cotidiana que puedan suponer un reto para sus capacidades cognitivas. Estos datos recogidos se envían estandarizados a un servidor para su almacenamiento y cuantificación. Nuestro objetivo es que la información resultante pueda ser utilizada por psicólogas expertas en este ámbito, para detectar de manera prematura detrimentos en las capacidades de personas mayores. Lo cual, pueda servir para evitar la evolución de problemas más graves, o para encontrar posibles soluciones a los ya encontrados. Siguiendo este proceso el trabajo podría aportar beneficios terapéuticos a las personas mayores

Hardware Reuse Improvement through the Domain Specific Language dHDL.

The dHDL language has been defined to improve hardware design productivity. This is achieved through the definition of a better reuse interface (including parameters, attributes and macroports) and the creation of control structures that help the designer in the hardware generation process

Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs

Linear regression is a technique widely used in digital signal processing. It consists on finding the linear function that better fits a given set of samples. This paper proposes different hardware architectures for the implementation of the linear regression method on FPGAs, specially targeting area restrictive systems. It saves area at the cost of constraining the lengths of the input signal to some fixed values. We have implemented the proposed scheme in an Automatic Modulation Classifier, meeting the hard real-time constraints this kind of systems have

Improving Hardware Reuse through XML-based Interface Encapsulation

This work proposes an encapsulation scheme aimed at simplifying the reuse process of hardware cores. This hardware encapsulation approach has been conceived with a twofold objective. First, we look for the improvement of the reuse interface associated with the hardware core description. This is carried out in a first encapsulation level by improving the limited types and configuration options available in the conventional HDLs interface, and also providing information related to the implementation itself. Second, we have devised a more generic interface focused on describing the function avoiding details from a particular implementation, what corresponds to a second encapsulation level. This encapsulation allows the designer to define how to configure and use the design to implement a given functionality. The proposed encapsulation schemes help improving the amount of information that can be supplied with the design, and also allow to automate the process of searching, configuring and implementing diverse alternatives