LDPC decoder architecture for DVB-S2 and DVB-S2X standards

International audienceA particular type of conflict due to multiple-diagonal sub-matrices in the DVB-S2 parity-check matrices is known to complicate the implementation of the layered decoder architecture. The new matrices proposed in DVB-S2X no longer use such sub-matrices. For implementing a decoder compliant both with DVB-S2 and DVB-S2X, we propose an elegant solution which overcomes this conflicts relying on an efficient write disable of the memories, allowing a straightforward implementation of layered LDPC decoders. The complexity and latency are further reduced by eliminating one barrel shifter. Compared with the existing solutions, complexity is reduced without performance degradation. Keywords—Low-Density Parity-Check (LDPC) code, memory conflict, layered decoder, DVB-S2, DVB-S2X

Before convergence early stopping criterion for inner LDPC code in DVB standards

International audienceThis letter presents a "before convergence" early stopping criterion for the LDPC decoder defined in the second generation of DVB standards. The idea is to stop the decoding process once the estimated number of remaining errors is below the maximum capacity correction of the outer BCH decoder used in the DVB-S2, T2 and C2 standards. Simulations show that the average number of iterations is reduced by up to 26% compared with classical early stopping criterion up to a frame error rate of 10^-6

NB-LDPC check node with pre-sorted input

International audienceNon-binary low-density parity-check codes have better communication performance compared to their binary counterparts but they suffer from higher complexity, especially for the check node processing. In this paper a sorting of the input vectors based on a reliability criteria is performed prior to the check node processing. This presorting process allows the Extended Min-Sum (EMS) check node process to focus its effort mainly on the weakest inputs. Proof is given for a check node of degree 12 in GF(64) for the syndrome based algorithm with a number of computed syndromes reduced by a factor of four which directly impacts the check node complexity without performance degradation. Index Terms—NB-LDPC, Check Node, syndrome-based, EMS

Intuitive human interactive with an arm robot for severely handicapped people - A one click approach.

International audienceAssistance to disabled people is still a domain in which a lot of progress needs to be done. The more severe the handicap is, more complex are the devices, implying increased efforts to simplify the interactions between man and these devices. In this document we propose a solution to reduce the interaction between a user and a robotic arm. The system is equipped with two cameras. One is fixed on the top of the wheelchair (eye-to-hand) and the other one is mounted on the end effector of the robotic arm (eye-in-hand). The two cameras cooperate to reduce the grasping task to one click. The method is generic, it does not require marks on the object, geometrical model or the database. It thus provides a tool applicable to any kind of graspable object. The paper first gives an overview of the existing grasping tools for disabled people and proposes a novel approach toward an intuitive human machine interaction

HIGH-SPEED CONFLICT-FREE LAYERED LDPC DECODER FOR THE DVB-S2, -T2 AND -C2 STANDARDS

International audienceLayered decoding is known to provide efficient and highthroughput implementation of LDPC decoders. However, the implementation of layered architecture is not always straightforward because of memory update conflicts in the a posteriori information memory. In this paper, we focus our attention on a particular type of conflict that is due to multiple-diagonal sub-matrices in the DVB-S2, -T2 and -C2 parity-check matrices. We propose an original solution that combines repetition of the concerned layers and the write disable of the a posteriori information memory. The implementation of this solution on an FPGA-based LDPC decoder led to an average air throughput of 200 Mbit/s with a parallelism of 45 and a clock frequency of 300 MHz. Increasing the parallelism to 120 led to an average air throughput of 720 Mbit/s with a clock frequency of 400 MHz on CMOS technology

Hardware Discrete Channel Emulator

International audienceIn this paper, the emulation environment named Hardware Discrete Channel Emulator (HDCE) has been developed as a coherent framework to emulate on a hardware device (FPGA as the implementation platform in the verification) and simulate on a computer the effect of an Additive White Gaussian Noise (AWGN) in a base band channel. The HDCE is able to generate more than 180 M samples per second for a very low hardware cost, which has been achieved in an efficient architecture. Using the HDCE, the performance evaluation of a coding scheme for a BER of 10−9 requires only one minute of emulation time

Active rough shape estimation of unknown objects

International audienceThis paper presents a method to determine the rough shape of an object. This is a step in the development of a One Click Grasping Tool, a grasping tool of everyday-life objects for an assistant robot dedicated to elderly or disabled. The goal is to determine the quadric that approximates at best the shape of an unknown object using multi-view measurements. Non-linear optimization techniques are considered to achieve this goal. Since multiple views are necessary, an active vision process is considered in order to minimize the uncertainty on the estimated parameters and determine the next best view. Finally, results that show the validity of the approach are presented

Vision-based grasping of unknown objects to improve disabled people autonomy.

International audienceThis paper presents our contribution to vision based robotic assistance for people with disabilities. The rehabilitative robotic arms currently available on the market are directly controlled by adaptive devices, which lead to increasing strain on the user's disability. To reduce the need for user's actions, we propose here several vision-based solutions to automatize the grasping of unknown objects. Neither appearance data bases nor object models are considered. All the needed information is computed on line. This paper focuses on the positioning of the camera and the gripper approach. For each of those two steps, two alternative solutions are provided. All the methods have been tested and validated on robotics cells. Some have already been integrated into our mobile robot SAM

Simplified Compression of Redundancy Free Trellis Sections in Turbo Decoder

International audienceIt has been recently shown that a sequence of R=q(M-1) redundancy free trellis stages of a recursive convolutional decoder can be compressed in a sequence of L=M-1 trellis stages, where M is the number of states of the trellis and q is a positive integer. In this paper, we show that for an M state Turbo decoder, among the L compressed trellis stages, only m = 3 or even m = 2 are necessary. The so-called $m$-min algorithm can either be used to increase the throughput for decoding a high rate turbo-code and/or to reduce its power consumption

Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders

International audienceLayered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of the layered architecture is not always straightforward because of the memory access conflicts in the a-posteriori information memory. In this paper, we focus our attention on a particular type of conflict introduced by the existence of multiple diagonal matrices in the DVB-T2 parity check matrix structure. We illustrate how the reordering of the matrix reduces the number of conflicts, at the cost of limiting the level of parallelism. We then propose a parity extending process to solve the remaining conflicts. Fixed point simulation results show coherent performance without modifying the layered architecture