Existence and regularity of solutions for an evolution model of perfectly plastic plates

We continue the study of a dynamic evolution model for perfectly plastic plates, recently derived from three-dimensional Prandtl-Reuss plasticity. We extend the previous existence result by introducing non-zero external forces in the model, and we discuss the regularity of the solutions thus obtained. In particular, we show that the first derivatives with respect to space of the stress tensor are locally square integrable

Design Productivity of a High Level Synthesis Compiler versus HDL

International audienceThe complexity of hardware systems is currently growing faster than the productivity of system designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description. The proposed Design Productivity metric evaluates the trade-off between design efficiency and implementation quality. The method is generic enough to be used for comparing several HLS methods of different natures, opening opportunities for further progress in Design Productivity. To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed. Versions of the sub-pixel interpolation filter from the MPEG HEVC standard are implemented and a design productivity gain of 2.3× in average is measured for the CAPH HLS method. It results from an average gain in design time of 4.4× and an average loss in quality of 1.9×

Distributed FPGA-based smart camera architecture for computer vision applications

International audienceSmart camera networks (SCN) raise challenging issues in many fields of research, including vision processing, communication protocols, distributed algorithms or power management. Furthermore, application logic in SCN is not centralized but spread among network nodes meaning that each node must have to process images to extract significant features, and aggregate data to understand the surrounding environment. In this context, smart camera have first embedded general purpose processor (GPP) for image processing. Since image resolution increases, GPPs have reached their limit to maintain real-time processing constraint. More recently, FPGA-based platforms have been studied for their massive parallelism capabilities. This paper present our new FPGA-based smart camera platform supporting cooperation between nodes and run-time updatable image processing. The architecture is based on a full reconfigurable pipeline driven by a softcore

Lightweight error correction technique in industrial IEEE802.15.4 networks

Industrial Wireless Sensor Networks (IWSNs) are nowadays becoming more and more popular thanks to their flexibility and pervasive monitoring capabilities to support process automation and remote maintenance applications. In such a scenario, channel errors due to the wireless medium can result in data packet losses, and consequently in unreliable IWSN services. To mitigate the above reported problem, this paper presents a lightweight error correction scheme specially developed for IEEE802.15.4-based IWSNs. By adding error correction and detection information inside the IEEE802.15.4 MAC data frame, the proposed FEC scheme is able to guarantee a backward compatibility with the standard while providing advanced capabilities in recovering data packets affected by bit errors. In the paper the benefits of the proposed technique are first evaluated through simulated loss traces, then they are validated in a real environment by considering real loss traces collected in an electricity power plant. The proposed error correction scheme is able to recover around 50% of the data packets that would be lost in case of a standard communication without any error correction capability

DreamCAM: A FPGA-based platform for smart camera networks

International audience—The main challenges in smart camera networks come from the limited capacity of network communications. Indeed, wireless protocols such as the IEEE 802.15.4 protocol target low data rate, low power consumption and low cost wireless networking in order to fit the requirements of sensor networks. Since nodes more and more often integrate image sensors, network bandwidth has become a strong limiting factor in application deployment. This means that data must be processed at the node level before being sent on the network. In this context, FPGA-based platforms, supporting massive data parallelism, offer large opportunities for on-board processing. We present in this paper our FPGA-based smart camera platform, called DreamCam, which is able to autonomously exchange processed information on an Ethernet network

HOG-Dot: A Parallel Kernel-Based Gradient Extraction for Embedded Image Processing

International audienceIn this paper we propose HOG-Dot, a method for the direct computation of the polar image gradients coordinates from the pixels values. The proposed algorithm, to be used as the first step of the Histogram of Oriented Gradient (HOG) pipeline, approximates the exact gradient with its projection onto a versor chosen among the projection plane set. Instead of non linear computations, the HOG-Dot method exploits linear operations while introducing a bounded approximation error with respect to other HOG approaches, thus resulting a more suitable solution for embedded devices. Concerning the state of the art, it also achieves improved accuracy with the mathematical spatial gradient formulation

Models of Architecture

The current trend in high performance and embedded computing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In state of the art Model Driven Engineering (MDE) methods, different communities have developed custom architecture models associated to languages of substantial complexity. This fact contrasts with Models of Computation (MoCs) that provide abstract representations of an algorithm behavior as well as tool interoperability.In this report, we define the notion of Model of Architecture (MoA) and study the combination of a MoC and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. An MoA provides reproducible cost computation for evaluating the efficiency of a system. A new MoA called Linear System-Level Architecture Model (LSLA) is introduced and compared to state of the art models. LSLA aims at representing hardware efficiency with a linear model. The computed cost results from the mapping of an application, represented by a model conforming a MoC on an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communication-related part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency

Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems

International audienceThe current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communication-related part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency

Parallel Image Gradient Extraction Core For FPGA-based Smart Cameras

International audienceOne of the biggest efforts in designing pervasive Smart Camera Networks (SCNs) is the implementation of complex and computationally intensive computer vision algorithms on resource constrained embedded devices. For low-level processing FPGA devices are excellent candidates because they support massive and fine grain data parallelism with high data throughput. However, if FPGAs offers a way to meet the stringent constraints of real-time execution, their exploitation often require significant algorithmic reformulations. In this paper, we propose a reformulation of a kernel-based gradient computation module specially suited to FPGA implementations. This resulting algorithm operates on-the-fly, without the need of video buffers and delivers a constant throughput. It has been tested and used as the first stage of an application performing extraction of Histograms of Oriented Gradients (HOG). Evaluation shows that its performance and low memory requirement perfectly matches low cost and memory constrained embedded devices

Isocitrate dehydrogenase 1 mutations (IDH1) and p16/CDKN2A copy number change in conventional chondrosarcomas.

To determine whether IDH1 mutations are present in primary and relapsed (local and distal) conventional central chondrosarcomas; and secondly, to assess if loss of p16/CDKN2A is associated with tumour grade progression, 102 tumour samples from 37 patients, including material from presenting and relapse events, were assessed. All wild-type cases for IDH1 R132 substitutions were also tested for IDH2 R172 and R140 alterations. The primary tumour and the most recent relapse sample were tested for p16/CDKN2A by interphase fluorescence in situ hybridisation. An additional 120 central cartilaginous tumours from different patients were also tested for p16/CDKN2A copy number. The study shows that if an IDH1 mutation were detected in a primary central chondrosarcoma, it is always detected at the time of presentation, and the same mutation is detected in local recurrences and metastatic events. We show that p16/CDKN2A copy number variation occurs subsequent to the IDH1 mutation, and confirm that p16/CDKN2A copy number variation occurs in 75 % of high grade central chondrosarcomas, and not in low grade cartilaginous tumours. Finally, p16/CDKN2A copy number variation is seen in both the IDH1 wild-type and mutant cartilaginous central tumours