Bake-hardening of dual-phase steels

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Effect of Current Density on Microstructure of Mn-Cu Thin Films produced by Electroplating Coating Technique

In the present study, 304 stainless steel (SS) was electrochemically plated with nanocrystalline Mn-Cu alloy coatings from a bath containing ammonium sulfate. The effects of current density on the microstructure, crystallographic structure, and chemical composition of the deposits were studied. The results showed that at low current densities, discontinuous coatings with a large amount of Cu can be obtained. Further increase in current density resulted in amorphous, compact and heterogeneous coatings with a small amount of Cu. The presence of Cu at low contents in precipitated coatings delayed the phase transformation of as-deposited ductile g-Mn to the brittle and hard a-Mn. However, the results did not show any specific changes in the grain size of the coatings with variation of current densities

Low power IC design characterization techniques under process variations

To overcome the increasing sensitivity to variability in nanoscale integrated circuits, operation parameters (e.g., supply voltage) are adapted in a customized way exclusively to each chip. AVS is a standard industrial technique which has been adopted widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits. For cost and complexity reasons, AVS techniques are usually implemented by means of on-chip performance monitors (so-called PMBs) allowing fast performance evaluation during production or run time. Such on-chip monitoring approaches estimate operation parameters either based on responses from performance monitors with no interaction with the circuit or by monitoring the actual critical paths of the circuit. In this thesis, we focus on AVS techniques, which estimate operation parameters using responses from on-chip performance monitors with no interaction with the circuit during production. We discuss the challenges that these monitoring methodologies face with decreasing node sizes, in terms of accuracy and effectiveness. We show that the accuracy of these approaches is design dependent, and requires up to 15% added design margin. In addition, we show using silicon measurements of a nanometric FD-SOI device that the required design margin is above 10% of the clock cycle, which leads to significant waste of power. In this thesis, we introduce the new method of using delay test patterns including TF, SDD, and PDLY test patterns for application of AVS during IC production. The proposed method is able to eliminate the need for PMBs, while improving the accuracy of performance estimation. The basic requirement of using delay-based AVS is that there should be a reasonable correlation between the frequency the chip can attain while passing all delay test patterns and the actual frequency of the chip. Based on simulation results of ISCAS’99 benchmarks with a 28 nm FD-SOI library, using delay test patterns result in an error of 5.33% for TF testing, an error of 3.96% for SDD testing, and an error as low as 1.85% using PDLY testing. Accordingly, PDLY patterns have the capacity to achieve the lowest error in performance estimation, followed by SDD patterns and finally TF patterns. We performed the same analysis using a 65 nm technology node, which showed the same results. We also did two different silicon measurements on a 28 nm FD-SOI CPU to investigate the effectiveness of the TF-based approach. The results of the first case study on real silicon comparing the performance estimation using functional test patterns and the TF-based approach show a very close correlation between the two, which proves the effectiveness of the TF approach. The second case study compares the accuracy of voltage estimation using PMBs and the TF-based approach. The results show that the PMB approach can only account for 85% of the uncertainty in voltage measurements, which results in considerable power waste. In comparison, the TF-based approach can account for 99% of that uncertainty, thereby providing the ability to reducing that wasted power.Computer Engineerin

Bake-hardening of dual-phase steels

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Synthesis and Characterization of Molybdenum Disulfide Composite Coating on Steel Using Chemical Vapor Deposition

Molybdenum disulfide (MoS2 ) is one of the most widely used solid lubricants applied in different ways on the surfaces under friction. In this work, AISI 316 austenitic stainless steel was coated with MoS2 , using chemical vapor deposition (CVD) at four different temperatures (400, 500, 600 and 700°C). Coatings properties were investigated using SEM, EDX, XRD and FTIR, Hardness Tester and Roughness tester. The results showed that with simultaneous evaporation of sulfur and molybdenum trioxide (MoO3 ) in the CVD chamber, a uniform coating layer containing MoS2 and MoO2 phases was formed. Increase in the substrate temperature resulted in the rise in the amount of MoS2 to MoO2 phases. The thickness, grain size and the hardness of the coating were 17-29 μm, 50-120 nm and 260-480 HV respectively. Friction tests carried out using pin-on-plate method under normal loads of 10 N under ambient conditions showed values of the friction coefficient 0.25-0.40

Molybdenum Disulfide (MoS2) Coating on AISI 316 Stainless Steel by Thermo-Diffusion Method

Molybdenum disulfide (MoS2) is one of the most widely used solid lubricants applied in different ways on the surfaces under friction. In this work, AISI 316 austenitic stainless steel was coated with MoS2, using thermo-diffusion method at different temperatures and times. Coatings properties were investigated using SEM, EDX, XRD and FTIR, Hardness Tester and Roughness tester. The results illustrated the formation of a uniform layer on the surface, containing MoS2 and MoO3-X phases. The thickness, grain size and the hardness of the coatings were 20-50 μm, 400-1000 nm and 350- 550 HV respectively. Friction tests carried out using ball-on-disc method under normal loads of 10 N under ambient conditions showed values of the friction coefficient 0.30-0.40. In addition, the kinetics of diffusion layers between the substrate and the coating were also investigated. It was found that there at steady temperature there is a parabolic relationship between the thickness of the diffusion layer and the treatment time. The activation energy for the process was estimated to be 143 kJ mol−1. Depending on the treatment time and temperature, the thicknesses of diffusion layer varied between 0.5 and 2.5 microns

Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

With the continued down-scaling of IC technology and increase in manufacturing process variations, it is becoming ever more difficult to accurately estimate circuit performance of manufactured devices. This poses significant challenges on the effective application of adaptive voltage scaling (AVS) which is widely used as the most important power optimization method in modern devices. Process variations specifically limit the capabilities of Process Monitoring Boxes (PMBs), which represent the current industrial state-of-the-art AVS approach. To overcome this limitation, in this paper we propose an alternative solution using delay testing, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS’99 benchmarks with 28nm FD-SOI library, that using delay test patterns result in an error of 5.33% for transition fault testing (TF), error of 3.96% for small delay defect testing (SDD), and an error as low as 1.85% using path delay testing (PDLY). In addition, the paper also shows the impact of technology scaling on the accuracy of delay testing for performance estimation during production. The results show that the 65nm technology node exhibits the same trends identified for the 28nm technology node, namely that PDLY is the most accurate, while, TF is the least accurate performance estimator.Computer Engineerin

Extended curettage versus en bloc resection for the treatment of grade 3 giant cell tumour of the knee with pathologic fracture: a retrospective study

Purpose: For the treatment of giant cell tumour of the bone (GCTB) around the knee, preserving the native joint confers advantages over scarifying it. But, there is a controversy about the efficacy of intralesional curettage versus en bloc resection for treatment of such lesions. In this study, we compared local recurrence, functional outcomes, and complications of extended curettage and en bloc resection in these lesions. Methods: Patients with grade 3 GCTB of the distal femur or proximal tibia who were presented with a pathologic fracture and treated with either en bloc resection (n = 22) or extended curettage (n = 20) were included. The mean follow-up of the patients was 6.4 ± 1.9 years in the resection group and 5.5 ± 2.4 years in the extended curettage group. The primary outcome was a local recurrence. Secondary outcomes were limb function evaluated by the Musculoskeletal Tumor Society (MSTS) score and rate of complications. Results: Local recurrence was seen in four (20) patients of the curettage group and three (13.7) patients of the resection group (P = 0.69). The mean MSTS score was 24 ± 1.9 in the resection group and 26.5 ± 1.3 in the curettage group (P < 0.001). The number of complications was not significantly different between the two study groups (P = 0.49). However, the number of complications that required revision surgery was significantly more in the resection group (P = 0.049). Conclusion: In grade 3 GCTB around the knee with pathologic fracture, extended curettage results in comparable oncologic outcomes to en bloc resection, while providing better function and a lower rate of revision. © 2020, SICOT aisbl