Direct Graphene Growth on Insulator

Fabrication of graphene devices is often hindered by incompatibility between the silicon technology and the methods of graphene growth. Exfoliation from graphite yields excellent films but is good mainly for research. Graphene grown on metal has a technological potential but requires mechanical transfer. Growth by SiC decomposition requires a temperature budget exceeding the technological limits. These issues could be circumvented by growing graphene directly on insulator, implying Van der Waals growth. During growth, the insulator acts as a support defining the growth plane. In the device, it insulates graphene from the Si substrate. We demonstrate planar growth of graphene on mica surface. This was achieved by molecular beam deposition above 600{\deg}C. High resolution Raman scans illustrate the effect of growth parameters and substrate topography on the film perfection. Ab initio calculations suggest a growth model. Data analysis highlights the competition between nucleation at surface steps and flat surface. As a proof of concept, we show the evidence of electric field effect in a transistor with a directly grown channel.Comment: 13 pages, 6 figure

Large scale graphene integration for silicon technologies

The main guarantor of success for silicon based semiconductor research and industry was the availability and continuous improve of wafer fabrication processes for large scale integration. New material integration in a stable and reliable silicon process platform has to face several challenges. Graphene as a 2D material is considered as a material with formidable properties. This can enable new functionalities and performance improvements in a large variety of applications. Using graphene devices in microelectronics requires beside appropriate performances certain techniques for large scale fabrication of graphene which are currently not yet in place. In this paper we present recent progress of process platform developments to enable wafer scale integration in a silicon cmos platform. Synthesis of graphene on silicon cmos compatible substrates are considered to fulfill a basic request for the integration of graphene related devices in a silicon environment with no risk of metallic cross contamination. We present recent results of graphene synthesis on Ge(100) and Ge (110). Therefore chemical vapor deposition (CVD) methods are used to realize Ge/Si substrates followed by a CVD graphene synthesis at ~890°C (1,2). Due to silicon diffusion inside germanium certain germanium thickness is required to allow the subsequent graphene process. We present high quality graphene on a 200mm silicon wafers with high uniformity, a 2D/G ratio of ~3 and low D mode over the entire 200mm wafer measured by Raman spectroscopy (Figure 1). To enable a selective graphene synthesis on a 200mm wafer we discuss first approaches of graphene growth on patterned germanium island. Please click Additional Files below to see the full abstract

Charge transfer and trapping as origin of a double dip in the transfer characteristics of graphene based field-effect transistors

We discuss the origin of an additional dip other than the charge neutrality point observed in transfer characteristics of graphene-based field-effect transistors. The double-dip is proved to arise from charge transfer between graphene and metal electrodes, while charge storage at the graphene/SiO2 interface enhances it. Considering different Fermi energy from the neutrality point along the channel and partial charge pinning at the contacts, we propose a model which explains all features in gate voltage loops.Comment: 14 pages, 5 figure

Perfluorodecyltrichlorosilane-based seed-layer for improved chemical vapour deposition of ultrathin hafnium dioxide films on graphene

We investigate the use of perfluorodecyltrichlorosilane-based self-assembled monolayer as seeding layer for chemical vapour deposition of HfO2 on large area CVD graphene. The deposition and evolution of the FDTS-based seed layer is investigated by X-ray photoelectron spectroscopy, Auger electron spectroscopy, and transmission electron microscopy. Crystalline quality of graphene transferred from Cu is monitored during formation of the seed layer as well as the HfO2 growth using Raman spectroscopy. We demonstrate that FDTS-based seed layer significantly improves nucleation of HfO2 layers so that graphene can be coated in a conformal way with HfO2 layers as thin as 10 nm. Proof-of-concept experiments on 200 mm wafers presented here validate applicability of the proposed approach to wafer scale graphene device fabrication

A Graphene-based Hot Electron Transistor

We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call Graphene Base Transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 50.000.Comment: 18 pages, 6 figure

Graphene field effect transistors with Niobium contacts and asymmetric transfer characteristics

We fabricate back-gated field effect transistors using Niobium electrodes on mechanically exfoliated monolayer graphene and perform electrical characterization in the pressure range from atmospheric down to 10-4 mbar. We study the effect of room temperature vacuum degassing and report asymmetric transfer characteristics with a resistance plateau in the n-branch. We show that weakly chemisorbed Nb acts as p-dopant on graphene and explain the transistor characteristics by Nb/graphene interaction with unpinned Fermi level at the interface.Comment: 10 pages, Research Pape

Graphene Grown on Ge(001) from Atomic Source

Among the many anticipated applications of graphene, some - such as transistors for Si microelectronics - would greatly benefit from the possibility to deposit graphene directly on a semiconductor grown on a Si wafer. We report that Ge(001) layers on Si(001) wafers can be uniformly covered with graphene at temperatures between 800{\deg}C and the melting temperature of Ge. The graphene is closed, with sheet resistivity strongly decreasing with growth temperature, weakly decreasing with the amount of deposited C, and reaching down to 2 kOhm/sq. Activation energy of surface roughness is low (about 0.66 eV) and constant throughout the range of temperatures in which graphene is formed. Density functional theory calculations indicate that the major physical processes affecting the growth are: (1) substitution of Ge in surface dimers by C, (2) interaction between C clusters and Ge monomers, and (3) formation of chemical bonds between graphene edge and Ge(001), and that the processes 1 and 2 are surpassed by CH$_{2}$ surface diffusion when the C atoms are delivered from CH$_{4}$. The results of this study indicate that graphene can be produced directly at the active region of the transistor in a process compatible with the Si technology

Bilayer Insulator Tunnel Barriers for Graphene-Based Vertical Hot-electron Transistors

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as the electron emitter in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transports. High injected tunneling current densities approaching 10$^3$ A/cm$^2$ (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm-thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO$_2$) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices