PixFEL: development of an X-ray diffraction imager for future FEL applications

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA output is processed by a time-variant shaper performing gated integration and correlated double sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel cameras at FELs) imager

CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging

A 3D, through silicon via microelectronic process, capable of face-to-face assembling two 130 nm CMOS tiers in a single bi-layer wafer, has been exploited for the design of monolithic active pixels (MAPS), featuring a deep N-well (DNW) collecting electrode. They are expected to improve on planar CMOS DNW MAPS in terms of charge collection efficiency since most of the PMOS transistors in the front-end electronics, with their N-wells, can be moved to a different layer from that of the DNW sensor. The vertical integration process also requires that one of the two CMOS tiers be thinned down to a mere 6 m to expose the through silicon vias and contact the sandwiched circuits. In this work, results from device simulations of 3D MAPS will be presented. The aim is to evaluate the potential of such a thin sensitive substrate in the detection of low energy particles (in the tens of keV range), in view of possible applications to biomedical imaging

The analog signal processor of the Auger fluorescence detector prototype

The Auger Fluorescence Detector will allow to determine the longitudinal development of atmospheric showers in the range 10 19 –10 21 eV. A detector module comprises an array of 20 � 22 PMTs at the focal surface of a large-aperture telescope. Thirty such modules will be used. The PMTs pixel signal is variable in shape depending on the shower-eye geometry. The sky background light (BL) is also variable. We have developed an analog signal processor to obtain best energy and timing resolution despite those constrains. The Head Electronics (HE) bias the PMTs and keeps its pulsegain constant even for large BL. This is measured using a current-monitor of novel design. Both the signal pulse and the BL DC level are sent via a single twisted pair to the Analog Board (AB). The AB performs the compression of the 15–16 bit signal dynamic range into 12 bits of the FADC which follows the AB. A three-pole Bessel filter was adopted for antialiasing. The AB includes 16 bit sigma-delta chips to readout the BL DC level, and a test-pulse distribution system. # 2001 Elsevier Science B.V. All rights reserved. PACS: 29.4

Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC

CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 μm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4μA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper

First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35x35 um2. ENC value is below 100e- for an input capacitance of 50 fF and in-time threshold below 1000e-. Leakage current compensation up to 50 nA with power consumption below 5 uW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 us. The total power consumption per pixel is below 5uW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper

Research and Design of a Routing Protocol in Large-Scale Wireless Sensor Networks

无线传感器网络，作为全球未来十大技术之一，集成了传感器技术、嵌入式计算技术、分布式信息处理和自组织网技术，可实时感知、采集、处理、传输网络分布区域内的各种信息数据，在军事国防、生物医疗、环境监测、抢险救灾、防恐反恐、危险区域远程控制等领域具有十分广阔的应用前景。 本文研究分析了无线传感器网络的已有路由协议，并针对大规模的无线传感器网络设计了一种树状路由协议，它根据节点地址信息来形成路由，从而简化了复杂繁冗的路由表查找和维护，节省了不必要的开销，提高了路由效率，实现了快速有效的数据传输。 为支持此路由协议本文提出了一种自适应动态地址分配算——ADAR（AdaptiveDynamicAddre...As one of the ten high technologies in the future, wireless sensor network, which is the integration of micro-sensors, embedded computing, modern network and Ad Hoc technologies, can apperceive, collect, process and transmit various information data within the region. It can be used in military defense, biomedical, environmental monitoring, disaster relief, counter-terrorism, remote control of haz...学位：工学硕士院系专业：信息科学与技术学院通信工程系_通信与信息系统学号：2332007115216

N and P-channel JFETs for low-noise and radiation hard analog applications

Dottorato di ricerca in ingegneria elettronica ed informatica. 12. ciclo. A.a. 1998-99. Tutore Valerio Re. Coordinatore Virginio CantoniConsiglio Nazionale delle Ricerche - Biblioteca Centrale - P.le Aldo Moro, 7, Rome; Biblioteca Nazionale Centrale - P.za Cavalleggeri, 1, Florence / CNR - Consiglio Nazionale delle RichercheSIGLEITItal