NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the 15 accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process

Reliable time exponents for long term prediction of negative bias temperature instability by extrapolation

To predict the negative bias temperature instability (NBTI) towards the end of pMOSFETs’ 10 years lifetime, power-law based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. The n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to 10 years. The objective of this work is to find how to make the n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps (AHT), a new method is proposed to capture the generated defects (GD) in their entirety. The n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under AC operation, the model predicts that GD can contribute to ~90% of NBTI at 10 years

ESD characterization of planar InGaAs devices

We present a comprehensive study of ESD reliability (TLP) on planar nMOSFETs with In0.53Ga0.47As as the channel material. Two types of traps are found during ESD stress. They are formed through independent mechanisms: transient Ef-lowering induced pre-existing e-traps discharging in the gate stack and hot hole induced e-traps generation through impact ionization in the InP buffer. These two types of traps explain the observed walk-out of off-state channel leakage current as well as the two-stage current conduction phenomena in the TLP measurement. The generated e-traps are permanent and can introduce detrimental conduction current harmful to the device performance. By properly selecting the buffer material, these defects can be removed

A Pragmatic Model to Predict Future Device Aging

To predict long term device aging under use bias, models extracted from voltage accelerated tests must be extrapolated into the future. The traditional model uses a power law, to linearly fit the test data on a log-log plot, and then extrapolates aging kinetics. The challenge is that the measured data do not always follow a straight line on the log-log plot, calling the accuracy of such prediction into question. Although there are models that can fit test data well in this case, their prediction capability for future aging is typically not verified. The key advance of this work is the development of a methodology for extracting models that can verifiably predict future aging over a wide (Vg, Vd) bias space, when aging kinetics do not follow a simple power law. This is achieved by experimentally separating aging into four types of traps and modelling each of them by a straight line individually. The applicability of this methodology is verified on 3 different CMOS processes where it can predict aging at least 3 orders of magnitude into the future. The contributions of each type of traps across the (Vg, Vd) space are mapped. It is also shown that good fitting with test data does not warrant good prediction, so that good fitting should not be used as the only criterion for validating a model

An ultra low voltage, low power, fully integrated VCO for GPS in 90 nm RF-CMOS

A fully integrated 0.6 V VCO for the GPS L1 band is realized in a 90 nm RF-CMOS process. The purpose of the design is to demonstrate how suitable deep submicron CMOS transistors are for ultra low voltage, low power oscillator design. The VCO operates at 6.3 GHz and a divide-by-four circuit buffer provide the wanted 1575.42 MHz signal. Measured phase noise is for a 0.6 V supply voltage and bias current of 2.6 mA - 122 dBc/Hz at 1 MHz offset, measured for a 1.58 GHz carrier. The phase noise of the VCO has been measured for different bias point showing good agreement between measured results and theory

A 0.6 V l .6 mW fully integrated voltage-controlled oscillator in 90 nm CMOS aiming for the GPS LI band

A fully integrated 0.6 V 2.6 mA VCO aimed for the GPS L1 band is realized in a 90 nm CMOS process. The VCO operates at 6.3 GHz and a divide-by-four circuit buffer provide the wanted 1575.42 MHz signal. The VCO has a measured phase noise of-103 dBc/Hz at 100kHz offset and a chip area of 1.15mm 2, including bondpads

Erosion properties of mud beds deposited in laboratory settling columns

Work has been conducted at Oxford University using H.R. Wallingford's Instrument for measuring Shear stress In Situ (ISIS). The first several experiments show that the equipment is working well in a column setup. Each bed tested is initially eroded by a distinct critical shear stress, or erosion threshold, which may depend on the properties of the mud and the length of consolidation time. The beds seem to erode in a laminar fashion, until at a very high shear rate a large (2 to 3 cm) liquified section of the surface gives way. Contrary to what might be expected, the beds become less resistant to erosion as they mature. It is proposed that the development of a biochemical surface layer, often containing gas, and the feeding and soil reworking by marine worms contribute to this weakening over time