An ART1 microchip and its use in multi-ART1 systems

Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, that chip rendered an extremely high silicon area consumption of 1 cm2, and consequently an extremely low yield of 6%. Redundant circuit techniques can be introduced to improve yield performance at the cost of further increasing chip size. In this paper we present an improved ART1 chip prototype based on a different approach to implement the most area consuming circuit elements of the first prototype: an array of several thousand current sources which have to match within a precision of around 1%. Such achievement was possible after a careful transistor mismatch characterization of the fabrication process (ES2-1.0 μm CMOS). A new prototype chip has been fabricated which can cluster 50-b input patterns into up to ten categories. The chip has 15 times less area, shows a yield performance of 98%, and presents the same precision and speed than the previous prototype. Due to its higher robustness multichip systems are easily assembled. As a demonstration we show results of a two-chip ART1 system, and of an ARTMAP system made of two ART1 chips and an extra interfacing chip

A modified ART 1 algorithm more suitable for VLSI implementations

This paper presents a modification to the original ART 1 algorithm (Carpenter and Grossberg, 1987a, A massively parallel architecture for a self-organizing neural pattern recognition machine, Computer Vision, Graphics, and Image Processing, 37, 54–115) that is conceptually similar, can be implemented in hardware with less sophisticated building blocks, and maintains the computational capabilities of the originally proposed algorithm. This modified ART 1 algorithm (which we will call here ART 1m) is the result of hardware motivated simplifications investigated during the design of an actual ART 1 chip [Serrano-Gotarredona et al., 1994, Proc. 1994 IEEE Int. Conf. Neural Networks (Vol. 3, pp. 1912–1916); Serrano-Gotarredona and Linares-Barranco, 1996, IEEE Trans. VLSI Systems, (in press)]. The purpose of this paper is simply to justify theoretically that the modified algorithm preserves the computational properties of the original one and to study the difference in behavior between the two approaches

A high-precision current-mode WTA-MAX circuit with multichip capability

This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), looser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication and comparison. Traditional techniques rely on the matching of an N transistors array, where N is the number of system inputs. This implies that when N increases, as the size of the circuit and the distance between transistors will also increase, transistor matching degradation and loss of precision in the overall system performance will result. Furthermore, when multichip systems are required, the transistor matching is even worse and performance is drastically degraded. The technique presented in this paper does not rely on the proper matching of N transistors, but on the precise replication and comparison of currents. This can be performed by current mirrors with a limited number of outputs. Thus, N can increase without degrading the precision, even if the system is distributed among several chips. Also, the different chips constituting the system can be of different foundries without degrading the overall system precision. Experimental results that attest these facts are presented

On the design and characterization of femtoampere current-mode circuits

In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is Implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-μm three-metal two-poly standard CMOS process.Ministerio de Ciencia y Tecnología TIC-1999-0446-C02-02, FIT-070000-2001-0859, TIC-2000-0406-P4-05, TIC-2002-10878-EEuropean Union IST-2001-3412

Log-domain implementation of complex dynamics reaction-diffusion neural networks

In this paper, we have identified a second-order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that implements the spatially discretized version of the selected reaction-diffusion equation. The logarithmic compression of the state variables allows several decades of variation of these state variables within subthreshold operation of the MOS transistors. Furthermore, as all the equation parameters are implemented as currents, they can be adjusted several decades. As a demonstrator, we have designed a chip containing a linear array of ten second-order dynamics coupled cells. Using this hardware, we have experimentally reproduced two complex spatio-temporal phenomena: the propagation of travelling waves and of trigger waves, as well as isolated oscillatory cells.Gobierno de España TIC1999-0446-C02-02Office of Naval Research (USA

7-decade tuning range CMOS OTA-C sinusoidal VCO

A new operational transconductance amplifier-capacitor (OTA-C) based sinusoidal voltage-controlled oscillator (VCO) has been designed and fabricated, the oscillation frequency of which can be tuned from 74 mHz to 1 MHz. The VCO uses a new OTA whose transconductance is adjusted by using a set of special current mirrors. These current mirrors operate in weak inversion and their gain can be controlled continuously through a gate voltage over many decades. This is the first report of such a wide tuning range for CMOS sinusoidal oscillators. Experimental results are provided

Reseña de libro: La teoría de las relaciones internacionales: una mirada desde el Sur

Llenderrozas, Elsa (coord.) Relaciones Internacionales: Teorías y debates EUDEBA, 2013 336 págs

Borders between permeability and “piquetes” (blockades). The social and territorial transformations in Posadas (Argentina) - Encarnación (Paraguay) during the nineties.

Las fronteras internacionales están experimentando cambios estructurales que afectan las formas de movilidad internacional. En el caso del paso fronterizo Posadas (Argentina)- Encarnación (Paraguay), entre 1990 y 1991 tres acontecimientos modificaron la función de control de la frontera: la inauguración del puente internacional, la firma del Tratado de Asunción y la aplicación de la ley de Convertibilidad (durante el gobierno de Carlos Menem). Como resultado la frontera se hizo más permeable y se alteraron las tradicionales movilidades internacionales: aumentó el comercio fronterizo por medio de actores –paseras, paseros, paquitos, puesteros, etcétera– y la circulación de posadeños hacia los negocios de Encarnación. Los comerciantes de la Cámara de Comercio e Industria de Posadas reclamaron un estricto control aduanero y entablaron una “lucha” en la frontera que culminó en dos “piquetes” en el puente internacional. Nuestro objetivo es mostrar la tensión entre la frontera material y simbólica a partir de dos aproximaciones: describiendo las transformaciones en el paso fronterizo PosadasEncarnación y sus consecuencias en las movilidades internacionales; y examinando la reacción a estas transformaciones en la protesta de los comerciantes posadeños, analizándolo en función de las discusiones actuales sobre los piquetes como forma de protesta social y la construcción de identidades/alteridades en la frontera.Borders between permeability and “piquetes” (blockades). The social and territorial transformations in Posadas (Argentina) - Encarnación (Paraguay) during the nineties. International borders are experiencing structural changes that affect the forms of international mobility. In the case of Posadas (Argentina) - Encarnación (Paraguay), between 1990 and 1991, three events modified the border control function: the inauguration of the international bridge, the signing of the Tratado de Asunción and the implementation of the Ley de Convertibilidad (during the government of Carlos Menem). As a result the border became more permeable and the traditional international mobilities were altered: the cross-border commerce done by the “paseras, paseros, paquitos” and “puesteros” and the circulation of posadeños towards the business of Encarnación were increased. The merchants of the Cámara de Comercio e Industria of Posadas demanded a strict customs control and engaged in a “fight” in the border that culminated in two “pickets” at the international bridge. Our objective is to show the tension between the material and symbolic border from two approaches: describing the border transformations in PosadasEncarnación and its consequences for the international mobilities; and examining the reaction to these transformations in the protest of the posadeño merchants, analyzing it in terms of the current discussion about the “pickets” as a form of social protest and the construction of identities/alterities at the border.Fil: Linares, María Dolores. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Saavedra 15. Instituto Multidisciplinario de Historia y Ciencias Humanas; Argentina. Ecole Des Hautes Etudes En Sciences Sociales; Francia. Universidad de Buenos Aires; Argentin

Low power LVDS transceiver for AER links with burst mode operation capability

This paper presents the design and simulation of an LVDS transceiver intended to be used in serial AER links. Traditional implementations of LVDS serial interfaces require a continuous data flow between the transmitter and the receiver to keep the synchronization. However, the serial AER-LVDS interface proposed in [2] operates in a burst mode, having long times of silence without data transmission. This can be used to reduce the power consumption by switching off the LVDS circuitry during the pauses. Moreover, a fast recovery time after pauses must be achieved to not slow down the interface operation. The transceiver was designed in a 90 nm technology. Extensive simulations have been performed demonstrating a 1 Gbps data rate operation for all corners in post-layout simulations. Driver and receiver take up an area of 100x215 m2 and 100x140 m2 respectively.Unión Europea 216777 (NABAB)Ministerio de Ciencia y Tecnología TEC2006-11730-C03-01 (SAMANTA II)Junta de Andalucía P06-TIC-0141

A programmable VLSI filter architecture for application in real-time vision processing systems

An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach is valid for any 2D filtering operation as long as the convolutional kernel F(p,q) is decomposable into an x-axis and a y-axis component, i.e. F(p,q)=H(p)V(q), for some rotated coordinate system [p,q]. If it is possible to find a coordinate system [p,q], rotated with respect to the absolute coordinate system a certain angle, for which the above decomposition is possible, then the proposed architecture is able to perform the filtering operation for any angle we would like the kernel to be rotated. This is achieved by taking advantage of the AER and manipulating the addresses in real time. The proposed architecture, however, requires one approximation: the product operation between the horizontal component H(p) and vertical component V(q) should be able to be approximated by a signed minimum operation without significant performance degradation. It is shown that for edge-extraction applications this filter does not produce performance degradation. The proposed architecture is intended to be used in a complete vision system known as the Boundary-Contour-System and Feature-Contour-System Vision Model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and electrical simulation and experimental results at the circuit level operation of some critical subcircuits