This paper presents the design and simulation of
an LVDS transceiver intended to be used in serial AER links.
Traditional implementations of LVDS serial interfaces require a
continuous data flow between the transmitter and the receiver
to keep the synchronization. However, the serial AER-LVDS
interface proposed in [2] operates in a burst mode, having long
times of silence without data transmission. This can be used
to reduce the power consumption by switching off the LVDS
circuitry during the pauses. Moreover, a fast recovery time after
pauses must be achieved to not slow down the interface operation.
The transceiver was designed in a 90 nm technology. Extensive
simulations have been performed demonstrating a 1 Gbps data
rate operation for all corners in post-layout simulations. Driver
and receiver take up an area of 100x215 m2 and 100x140 m2
respectively.Unión Europea 216777 (NABAB)Ministerio de Ciencia y Tecnología TEC2006-11730-C03-01 (SAMANTA II)Junta de Andalucía P06-TIC-0141
