Desarrollo de encriptado AES en FPGA

The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. Synthesis results in the use of 460 logic cells and 4480 memory bits. The VHDL code was simulated using the test vectors provided in the AES submission package. The results are functionally correct. The architecture needs fewer logic cells than other ciphers and uses as few memory blocks as possible. The design goals were area and cost optimisation.Facultad de Informátic

Minimum area, low cost fpga implementation of aes

The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost.Eje: IV - Workshop de procesamiento distribuido y paraleloRed de Universidades con Carreras en Informática (RedUNCI

Minimum area, low cost fpga implementation of aes

The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost.Eje: IV - Workshop de procesamiento distribuido y paraleloRed de Universidades con Carreras en Informática (RedUNCI

Decodificación de códigos LDPC en canal de Rayleigh con algoritmos genéticos

En este trabajo se propone la decodificación de Códigos Low Density Parity Check (LDPC) mediante un decodificador que utiliza una combinación de Algorimos Genéticos (GA, Genetic Algorithms) con Lógica Mayoritaria. La selección de GA obedece a la capacidad de los mismos para resolver problemas de optimización complejos, basándose en principios de la evolución natural de una población cuyos individuos se evalúan de acuerdo a una función de ajuste. El tipo de decodificación propuesto en este trabajo ha arrojado valores de Probabilidad Binaria de Error (BER, Bit Error Rate) comparables con la comportamiento del algoritmo tradicional de decodificación suma-producto para un canal de comunicaciones inalámbricas. La ventaja adicional de la decodificación propuesta frente a la tradicional es que no precisa conocer información de la relación Señal a Ruido en el canal.Sociedad Argentina de Informática e Investigación Operativ

Performance of a Simplified Soft-Distance decoding algorithm for LDPC codes over the Rayleigh fading channel

In this paper, we investigate the performance of a Soft-Input soft-Output decoding algorithm for LDPC codes that uses Euclidean distance as its metric, in the Rayleigh fading channel. It is found that its Bit Error Rate performance is close to that of traditional decoding algorithms like the SumProduct algorithm and its logarithmic version. Main characteristics of the proposed algorithm and its modification to perform over the Rayleigh channel are described. This algorithm uses squared Euclidean distance as the metric, does not require knowledge of the signal-to-noise ratio of the received signal, and is less complex to implement than other soft-input, soft-output algorithms.Fil: Arnone, Leonardo Jose. Universidad Nacional de Mar del Plata. Facultad de Ingeniería; ArgentinaFil: Liberatori, Mónica Cristina. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; ArgentinaFil: Petruzzi, David Mario. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; ArgentinaFil: Farrell, P. G.. Lancaster University. Department of Communications Systems; Reino UnidoFil: Castiñeira Moreira, Jorge. Universidad Nacional de Mar del Plata. Facultad de Ingenieria; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Mar del Plata; Argentin

Simulation of a non-invasive glucometer based on a microwave resonator sensor

In this paper a simulation of a microwave resonator sensor for constructing a noninvasive blood glucose meter is presented. A relationship between changes of the dielectric permittivity of the blood and the frequency response of S parameters of the sensor is observed. This can lead to a measuring procedure in which the glucose level present has a correlation with the value of the frequency resonance of the sensor. The test bank consists of a planar spiral microwave resonator over which the individual under test places his/her finger. This modifies the initial frequency resonance of the resonator because of the change produced in the measuring procedure over the dielectric permittivity of the resonator. Simulations show a correlation between dielectric permittivity blood changes, and changes in the value of the frequency resonance, in the frequency response of S parameters of the resonatorFil: Pimentel, Santiago. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; ArgentinaFil: Aguero, Pablo Daniel. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; ArgentinaFil: Uriz, Alejandro José. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Bonadero, Juan Carlos. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; ArgentinaFil: Liberatori, Mónica Cristina. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; ArgentinaFil: Castiñeira Moreira, Jorge. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Electrónica. Laboratorio de Comunicaciones; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentin

An Encryption and Error-Control Coding scheme based on Non binary LDPC codes

In this paper we present a combined error-control coding and encryption scheme that provides to a given system with both high levels of reliability of the transmission and security. These two aims are usually present in wireless data transmission systems. The scheme is based on efficient Non Binary Low Density Parity Check codes which were selected for this design because they outer perform their binary counterparts. By means of a set of operations over the parity check matrix of the code, encryption capabilities are added to the scheme, without producing any degradation in the corresponding Bit Error Rate performance, as usually happens when encryption and error control coding are applied separately.Sociedad Argentina de Informática e Investigación Operativ