The Role of Silicates in Interstitial Lung Disease

Interstitial Lung disease (ILD), produces disruption of alveolar walls with loss of functionality and accumulation of scar tissue. Asbestosis and silicosis are the ILD produced by the inhalation of asbestos fibers or silica particles respectively. An increase in prostacyclin release after exposing endothelial cells to asbestos has been reported. This study attempts to elucidate the role of lung epithelial cells in the generation of asbestos induced ILD. A cell model to study crocidolite-induced toxicity was developed using LA-4 cells, previously characterized as alveolar type II cells. LA-4 cells when exposed to crocidolite had a decrease in viability and an increase in the release of LDH and 6-keto PGF1α, a prostacyclin metabolite. Prostacyclin release was Cox 2 and vitronectin receptor (VNR) mediated. Coating crocidolite asbestos with vitronectin enhances its internalization via VNR, which also recognize the Arg-Gly-Asp (RGD) motif present in a variety of ligands (e.g., vitronectin, fibronectin). These findings propose that crocidolite is coated by an RGD protein and binds VNR inducing Cox 2 expression promoting prostacyclin release. Cytotoxicity did not follow the same model. In silica studies, it has been previously reported that Scavenger receptor A I/II (SR-A I/II) plays a role in silicainduced apoptosis. The cytoplasmic domain of the SR-AI/II has four aminoacids: Ser25, Ser32, Ser53, Thr34 that can be phosphorylated, and the extracellular region contains a lysine-rich cluster that is required for Acetylated Low density lipoprotein (AcLDL) binding. SR-AI contains a cysteine-rich domain, which is absent in SR-AII. This study evaluated the role of the four aminoacids that could be phosphorylated, and differences between SR-AI and SR-AII in silica binding. Constructs expressing SR-AII, and mutated SR-AIIs containing deletions to Ser25, Ser32, Ser53, Thr34 and KE (lysine cluster) were generated and CHO cells were transfected. Receptor functionality was verified by AcLDL uptake. Silica binding or silica-induced apoptosis was not statistically significant different from transfected controls. In addition, no statistically significant difference was found between SR-AI and SR-AII in AcLDL uptake, silica binding, and silica-induced apoptosis. This study shows that asbestos or silica alone cannot induce its effect, and asbestos required to be coated by RGD proteins

Turtle logic: Novel IC digital probabilistic design methodology

Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins are reduced, exposing computations to higher soft-error rates. In other words, the future circuits will be in a scenario where all devices may fail due to soft-error produced by trend of low SNR. In order to design reliable circuits with unreliable components, novel design techniques have been introduced. The problem of designing reliable systems with unreliable components traces back to Von Neumann, who proposed the N-tuple Modular Redundancy (NMR) technique. Additional proposals have appeared in the literature addressing the problem from the point of view of noise tolerance. For instance, the approach based on Markov Random Field theory (MRF). Take in account the Hamming distance for build basic logic gates focus to high noise and low voltage scenarios. Therefore, our proposal is based on the assumption that the devices in new and future technologies will be not perfect, noisy and hence they might fail.Peer ReviewedPostprint (published version

The advanced bedding sub-sector is strengthening in the Valencian Region

[EN] IBV supports the consolidation of the industrial growth that it is now taking place in the advanced bedding sub-sector in the Comunidad Valenciana. This support has been showed in the CAMATECH initiative, by firm technification, the objective control of product properties and value chain of the production.[ES] El IBV apoya la consolidación del crecimiento industrial que se está produciendo en el subsector del descanso avanzado en la Comunitat Valenciana. Este apoyo se ha concretado en el proyecto CAMATECH a través de la tecnificación de las empresas y el control objetivo de las propiedades del producto y de su cadena de valor.El proyecto CAMATECH se ha llevado a cabo con la colaboración de varias empresas representantes de la cadena de valor: COLCHONES DELAX, S.L., VISCOFORM, S. L., CAMPOS MONTAVERNER, S. L., FUNCOTEX S. L., SOMILAR SISTEMAS DE DESCANSO, S.L., SOMIQUEL, S.L., TAG INGENIEROS, S.L. Proyecto financiado por el Programa de acciones estratégicas de diversificación industrial para la Comunitat Valenciana de la Conselleria d’Industria, Comerç i Innovació. Cofinanciado por el Fondo Europeo de Desarrollo Regional, a través del Programa Operativo FEDER.Zamora Alvarez, TA.; López Torres, M.; Valero Martínez, M.; Huertas Leyva, P.; Serrano Ortiz, JF.; Matey González, FJ.; López López, J.... (2013). El sector del descanso avanzado se consolida en la Comunitat. Revista de biomecánica. 59:19-21. http://hdl.handle.net/10251/38666S19215

DVINO: A RISC-V vector processor implemented in 65nm technology

This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN).Peer ReviewedArticle signat per 43 autors/es: Guillem Cabo∗, Gerard Candón∗, Xavier Carril∗, Max Doblas∗, Marc Domínguez∗, Alberto González∗, Cesar Hernández†, Víctor Jiménez∗, Vatistas Kostalampros∗, Rubén Langarita∗, Neiel Leyva†, Guillem López-Paradís∗, Jonnatan Mendoza∗, Francesco Minervini∗, Julian Pavón∗, Cristobal Ramírez∗, Narcís Rodas∗, Enrico Reggiani∗, Mario Rodríguez∗, Carlos Rojas∗, Abraham Ruiz∗, Víctor Soria∗, Alejandro Suanes‡, Iván Vargas∗, Roger Figueras∗, Pau Fontova∗, Joan Marimon∗, Víctor Montabes∗, Adrián Cristal∗, Carles Hernández∗, Ricardo Martínez‡, Miquel Moretó∗§, Francesc Moll∗§, Oscar Palomar∗§, Marco A. Ramírez†, Antonio Rubio§, Jordi Sacristán‡, Francesc Serra-Graells‡, Nehir Sonmez∗, Lluís Terés‡, Osman Unsal∗, Mateo Valero∗§, Luís Villa† // ∗Barcelona Supercomputing Center (BSC), Barcelona, Spain. Email: [email protected]; †Centro de Investigación en Computación, Instituto Politécnico Nacional (CIC-IPN), Mexico City, Mexico; ‡ Institut de Microelectronica de Barcelona, IMB-CNM (CSIC), Spain. Email: [email protected]; §Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. Email: [email protected] (author's final draft

Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits

As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit reliability in the presence of faults and noise. The Turtle Logic (TL) is a new probabilistic logic method based on port redundancy and complementary data, oriented to emerging and beyond CMOS technologies. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic blocks or functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs, as well as intrinsic noise (thermal noise and flicker noise) and shot noise in the power source.Peer Reviewe

Turtle logic: Novel IC digital probabilistic design methodology

Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins are reduced, exposing computations to higher soft-error rates. In other words, the future circuits will be in a scenario where all devices may fail due to soft-error produced by trend of low SNR. In order to design reliable circuits with unreliable components, novel design techniques have been introduced. The problem of designing reliable systems with unreliable components traces back to Von Neumann, who proposed the N-tuple Modular Redundancy (NMR) technique. Additional proposals have appeared in the literature addressing the problem from the point of view of noise tolerance. For instance, the approach based on Markov Random Field theory (MRF). Take in account the Hamming distance for build basic logic gates focus to high noise and low voltage scenarios. Therefore, our proposal is based on the assumption that the devices in new and future technologies will be not perfect, noisy and hence they might fail.Peer Reviewe

A new probabilistic design methodology of nanoscale digital circuits

The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic design probabilistic methodology oriented to emerging and beyond CMOS in new technologies is presented, to improve tolerance to errors due to noise, defects or manufacturability errors in single gates, logic blocks or functional units. The methodology is based on the coherence of the input redundant ports using Port Redundancy (PR) and complementary redundant ports. Simulations show an excellent performance of our approach in the presence of large random noise at the inputs.Peer Reviewe

Turtle logic: Novel IC digital probabilistic design methodology

Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins are reduced, exposing computations to higher soft-error rates. In other words, the future circuits will be in a scenario where all devices may fail due to soft-error produced by trend of low SNR. In order to design reliable circuits with unreliable components, novel design techniques have been introduced. The problem of designing reliable systems with unreliable components traces back to Von Neumann, who proposed the N-tuple Modular Redundancy (NMR) technique. Additional proposals have appeared in the literature addressing the problem from the point of view of noise tolerance. For instance, the approach based on Markov Random Field theory (MRF). Take in account the Hamming distance for build basic logic gates focus to high noise and low voltage scenarios. Therefore, our proposal is based on the assumption that the devices in new and future technologies will be not perfect, noisy and hence they might fail.Peer Reviewe