Beyond Gbps Turbo Decoder on Multi-Core CPUs

International audienceThis paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K < 4096

MIPP: a Portable C++ SIMD Wrapper and its use for Error Correction Coding in 5G Standard

International audienceError correction code (ECC) processing has so far been performed on dedicated hardware for previous generations of mobile communication standards, to meet latency and bandwidth constraints. As the 5G mobile standard, and its associated channel coding algorithms , are now being specified, modern CPUs are progressing to the point where software channel decoders can viably be contemplated. A key aspect in reaching this transition point is to get the most of CPUs SIMD units on the decoding algorithms being pondered for 5G mobile standards. The nature and diversity of such algorithms requires highly versatile programming tools. This paper demonstrates the virtues and versatility of our MIPP SIMD wrapper in implementing a high performance portfolio of key ECC decoding algorithms

Energy Consumption Analysis of Software Polar Decoders on Low Power Processors

International audienceThis paper presents a new dynamic and fully generic implementation of a Successive Cancellation (SC) decoder (multi-precision support and intra-/inter-frame strategy support). This fully generic SC decoder is used to perform comparisons of the different configurations in terms of throughput, latency and energy consumption. A special emphasis is given on the energy consumption on low power embedded processors for software defined radio (SDR) systems. A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps. Some design guidelines are given in order to adapt the configuration to the application context

An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes

International audienceError Correction Code decoding algorithms for consumer products such as Internet of Things (IoT) devices are usually implemented as dedicated hardware circuits. As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to market. The recently introduced family of Successive Cancellation decoders for Polar codes has been shown in several research works to efficiently leverage the ubiquitous SIMD units in modern CPUs, while offering strong potentials for a wide range of optimizations. The P-EDGE environment introduced in this paper, combines a specialized skeleton generator and a building blocks library routines to provide a generic, extensible Polar code exploration workbench. It enables ECC code designers to easily experiments with combinations of existing and new optimizations , while delivering performance close to state-of-art decoders

A gene-based radiation hybrid map of chicken microchromosome 14: Comparison to human and alignment to the assembled chicken sequence

We present a gene-based RH map of the chicken microchromosome GGA14, known to have synteny conservations with human chromosomal regions HSA16p13.3 and HSA17p11.2. Microsatellite markers from the genetic map were used to check the validity of the RH map and additional markers were developed from chicken EST data to yield comparative mapping data. A high rate of intra-chromosomal rearrangements was detected by comparison to the assembled human sequence. Finally, the alignment of the RH map to the assembled chicken sequence showed a small number of discordances, most of which involved the same region of the chromosome spanning between 40.5 and 75.9 cR6000 on the RH map

A high-resolution radiation hybrid map of chicken chromosome 5 and comparison with human chromosomes

BACKGROUND: The resolution of radiation hybrid (RH) maps is intermediate between that of the genetic and BAC (Bacterial Artificial Chromosome) contig maps. Moreover, once framework RH maps of a genome have been constructed, a quick location of markers by simple PCR on the RH panel is possible. The chicken ChickRH6 panel recently produced was used here to construct a high resolution RH map of chicken GGA5. To confirm the validity of the map and to provide valuable comparative mapping information, both markers from the genetic map and a high number of ESTs (Expressed Sequence Tags) were used. Finally, this RH map was used for testing the accuracy of the chicken genome assembly for chromosome 5. RESULTS: A total of 169 markers (21 microsatellites and 148 ESTs) were typed on the ChickRH6 RH panel, of which 134 were assigned to GGA5. The final map is composed of 73 framework markers extending over a 1315.6 cR distance. The remaining 61 markers were placed alongside the framework markers within confidence intervals. CONCLUSION: The high resolution framework map obtained in this study has markers covering the entire chicken chromosome 5 and reveals the existence of a high number of rearrangements when compared to the human genome. Only two discrepancies were observed in relation to the sequence assembly recently reported for this chromosome

Fast Simulation and Prototyping with AFF3CT

International audienceThis demonstration intends to present AFF3CT (A Fast Forward 3rror Correction Tool). The main objective of AFF3CT is to provide a portable, open source, fast and flexible software to the channel coding community in such a way that researchers can spend more time on channel coding / algorithmic problems instead of software development issues. It is also intended to facilitate the process of hardware verification and debug with the objective of fast prototyping. I. SIMULATION OF A DIGITAL COMMUNICATION CHAIN Despite the wide variety of existing communication systems , all of them are based on a common abstract model that was proposed by the genius founder of information theory, Claude Shannon [1]. Figure 1 shows the synoptic of such a communication chain. In this structure, the channel encoder and decoder determine the achievable error rate of the system. Moreover, the channel decoder is a large contributor in the overall computational complexity of the system. On the eve of the 5th generation of mobile communication systems, one of the challenges is to imagine systems able to transmit a huge amount of data in a very short amount of time at a very small energy cost in a wide variety of environments. In such a context, researchers work at refining some existing coding schemes (encoder + decoder) in such a way that the system has a low residual error rate and that the associated decoder is fast, flexible and has a low complexity. The validation of a new coding scheme requires the estimation of the error rate performance. Unfortunately, most of the time, no simple mathematical model exists to predict the performance of a channel encoder/decoder. The only simple solution is to perform a Monte Carlo simulation of the whole communication chain: some data are pseudo-randomly generated, encoded, modulated, noised, decoded and the performance is estimated by measuring the Bit Error Rate (BER) and the Frame Error Rate (FER) at the receiver side. This apparently simple setup leads to three main problems. Reproducibility: It is usually a tedious task to reproduce the results from the literature. This can be explained by the large amount of empirical parameters necessary to define one communication system and not all of them are reported in the publications. Moreover, it is rare that researchers actually share the source code of their simulator. As a consequence, a large amount of time is spent "reinventing the wheel" only to be able to compare to the state-of-the-art results