Overlay Accuracy Limitations of Soft Stamp UV Nanoimprint Lithography and Circumvention Strategies for Device Applications

In this work multilevel pattering capabilities of Substrate Conformal Imprint Lithography (SCIL) have been explored. A mix & match approach combining the high throughput of nanoimprint lithography with the excellent overlay accuracy of electron beam lithography (EBL) has been exploited to fabricate nanoscale devices. An EBL system has also been utilized as a benchmarking tool to measure both stamp distortions and alignment precision of this mix & match approach. By aligning the EBL system to 20 mm x 20 mm and 8 mm x 8 mm cells to compensate pattern distortions of order of $3 \mu m$ over 6 inch wafer area, overlay accuracy better than $1.2 \mu m$ has been demonstrated. This result can partially be attributed to the flexible SCIL stamp which compensates deformations caused by the presence of particles which would otherwise significantly reduce the alignment precision

High Photocurrent in Gated Graphene-Silicon Hybrid Photodiodes

Graphene/silicon (G/Si) heterojunction based devices have been demonstrated as high responsivity photodetectors that are potentially compatible with semiconductor technology. Such G/Si Schottky junction diodes are typically in parallel with gated G/silicon dioxide (SiO$_2$)/Si areas, where the graphene is contacted. Here, we utilize scanning photocurrent measurements to investigate the spatial distribution and explain the physical origin of photocurrent generation in these devices. We observe distinctly higher photocurrents underneath the isolating region of graphene on SiO$_2$ adjacent to the Schottky junction of G/Si. A certain threshold voltage (V$_T$) is required before this can be observed, and its origins are similar to that of the threshold voltage in metal oxide semiconductor field effect transistors. A physical model serves to explain the large photocurrents underneath SiO$_2$ by the formation of an inversion layer in Si. Our findings contribute to a basic understanding of graphene / semiconductor hybrid devices which, in turn, can help in designing efficient optoelectronic devices and systems based on such 2D/3D heterojunctions.Comment: 25 pages, 5 figure

Reliable lift-off patterning of graphene dispersions for humidity sensors

Dispersion-based graphene materials are promising candidates for various sensing applications. They offer the advantage of relatively simple and fast deposition via spin-coating, Langmuir-Blodgett deposition, or inkjet printing. Film uniformity and reproducibility remain challenging in all of these deposition methods. Here, we demonstrate, characterize, and successfully apply a scalable structuring method for graphene dispersions. The method is based on a standard lift-off process, is simple to implement, and increases the film uniformity of graphene devices. It is also compatible with standard semiconductor manufacturing methods. We investigate two different graphene dispersions via Raman spectroscopy and Atomic Force Microscopy and observe no degradation of the material properties by the structuring process. Furthermore, we achieve high uniformity of the structured patterns and homogeneous graphene flake distribution. Electrical characterizations show reproducible sheet resistance values correlating with material quantity and uniformity. Finally, repeatable humidity sensing is demonstrated with van der Pauw devices, with sensing limits of less than 1% relative humidity.Comment: 35 page

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Graphene coating of Nafion(R)^{(R)} membranes for enhanced fuel cell performance

Electrochemically exfoliated graphene (e-G) thin films on Nafion$^{(R)}$ membranes exhibit a selective barrier effect against undesirable fuel crossover. The approach combines the high proton conductivity of state-of-the-art Nafion$^{(R)}$ and the ability of e-G layers to effectively block the transport of methanol and hydrogen. Nafion$^{(R)}$ membranes are coated with aqueous dispersions of e-G on the anode side, making use of a facile and scalable spray process. Scanning transmission electron microscopy (STEM) and electron energy-loss spectroscopy (EELS) confirm the formation of a dense percolated graphene flake network which acts as diffusion barrier. The maximum power density in direct methanol fuel cell (DMFC) operation with e-G coated Nafion$^{(R)}$ N115 is 3.9 times higher than the Nafion$^{(R)}$ N115 reference (39 vs. 10 mW cm$^{-2}$ @ 0.3 V) at 5M methanol feed concentration. This suggests the application of e-G coated Nafion$^{(R)}$ membranes for portable DMFCs, where the use of highly concentrated methanol is desirable

Residual Metallic Contamination of Transferred Chemical Vapor Deposited Graphene

Integration of graphene with Si microelectronics is very appealing by offering potentially a broad range of new functionalities. New materials to be integrated with Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etch and electrochemical delamination methods with respect to residual sub-monolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection x-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10$^{13}$ atoms/cm$^{2}$. These metal impurities appear to be partly mobile upon thermal treatment as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics these results reveal that further progress in synthesis, handling, and cleaning of graphene is required on the way to its advanced electronic and optoelectronic applications.Comment: 26 pages, including supporting informatio