Implementation of a Distributed Fault-Tolerant NoC-based Architecture for the Single-Event Upset Detector

Today, with the rise of the private sector in space exploration, space missions are becoming more frequent than before. This in relation to the fact that modern electronics scale both faster and denser, the effects of radiation become a critical design requirement for fault-tolerance in on-board space computer systems. Radiation damage can be separated into two categories, Total Ionizing Effects (TID) and Single Event Effects (SEE). Different approaches exist in different design levels when facing the radiation hostile environment of space. Most commonly space on-board electronics use radiation-hardened components, however, this solution holds back the possibilities of space exploration, as usually these components are two or three generations older and a few orders of magnitude more expensive. Space electronics are in need of a fault-tolerant architecture that can leverage the high performance and the low cost of commercial off-the-shelf (COTS) components since SEEs and TID can limit the lifespan of a mission. To investigate a Fault-Tolerant COTS based in-house solution, that can detect and mitigate SEUs, the Single-Event Upset Detector (SEUD) project was proposed by the department of Electronic Systems, at the Royal Institute of Technology (KTH), and will be hosted by the KTH MInature STudent (MIST) satellite. The hypothesis is based on the fact that modern, faster, COTS Field-Programmable-Gate-Arrays (FPGA) are highly susceptible to SEUs due to their SRAM-based physical design but provide advanced mitigation techniques such as partial reconfigurability (i.e. Artix-7) while other FPGAs are FLASH-based and offer SEU immune configuration memory (i.e. SmartFusion2) in trade-off to slower operating frequencies. The proposed architecture is composed of two FPGA devices connected together through an in-house, off-chip distributed, Network-On-Chip (NoC) solution. The SRAM-based FPGA will act as the proof of concept platform where in-house developed SEU mitigation techniques will be evaluated, while the flash-based FPGA will act as the supervisor of the experiment as well as handle the communication link with the On-Board Computer (OBC) of MIST. The architecture features TMR protected flash configuration memories as well as two COTS SDRAM memories connected to each FPGA. The real case scenario which the fault-tolerant architecture will be evaluated on, is the image acquisition from a hosted camera, the storage and compression of the image and finally its transmission to the OBC. This Thesis aims to contribute to the SEUD experiment by investigating three crucial features, the implementation of a novel SEU mitigation technique for COTS Synchronous Dynamic Access Memory (SDRAM) devices using a prototype ErrorDetection-And-Correction (EDAC) controller, the design and implementation of a prototype fault-tolerant communication bridge between the two FPGAs and finally the implementation of a 2x3 Mesh Nostrum Network-On-Chip (NoC) solution distributed over two physically separate FPGA chips

Ένοπλες Δυνάμεις και διαχείριση μεταναστευτικών/προσφυγικών ροών. Χαρακτηριστικά και τρόποι ανθρωπιστικής παρέμβασης»

Η διπλωματική εργασία έχει σαν αντικειμενικό σκοπό να εντοπίσει και να αναλύσει τα αίτια, αφορμές και τις παραμέτρους εμφάνισης του προσφυγικού ζητήματος, καθώς και του μεταναστευτικού και να μπορέσει εν μέρει να αναπτύξει/προτείνει τρόπους διαχείρισης των προσφυγικών ροών από τις Ελληνικές Ένοπλες Δυνάμεις, μέσα στα όρια του υφιστάμενου νομικού και θεσμικού πλαισίου του Συντάγματος της Ελληνικής Δημοκρατίας και να περιγράψει τα χαρακτηριστικά της ανθρωπιστικής παρέμβασης από αυτές.The objective of the Thesis is to identify and analyze the causes, reasons and parameters of the refugee issue, as well as immigration. This paper will try to develop and propose ways of managing the migrant refugee flows by the Greek Armed Forces, within the limits of the existing legal and institutional framework of the Constitution of the Hellenic Republic. The paper will try to describe the characteristics of humanitarian intervention by the Armed Forces

InterNoC: Unified Deterministic Communication For Distributed NoC-based Many-Core

Publication in Conference proceedings/Worksho

Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller

With the recent advancements in the Industrial Internet of Things and Industry 4.0, cyber-physical systems have become increasingly inter-connected. It is becoming a challenge to maintain the same quality-of-control and time-predictability of computation and communication required by safety-critical hard real-time systems as previously achieved through non-distributed architectures. This paper examines the problem of implementing and distributing a closed-loop command-control system over an Ethernet network with guaranteed timing bounds. To achieve bounded communication and computation time, we use an open-source software framework running on the T-CREST platform combined with a TTEthernet network star topology. We evaluate its quality-of-control performance in our experimental setup and compare the results against single-core and multi-core implementations. The proposed distributed time-triggered runtime system executes with jitter below 10µs and can perform a stable flight scenario as verified by the benchmark implementation

Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress

2020 International Conference on Embedded Software (EMSOFT 2020

Synchronizing Real-Time Tasks in Time-Triggered Networks

2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC

Fault-tolerant Clock Synchronization using Precise Time Protocol Multi-Domain Aggregation

2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC