Shear strength behavior of geotextile/geomembrane interfaces

This paper aims to study the shear interaction mechanism of one of the critical geosynthetic interfaces, the geotextile/geomembrane, typically used for lined containment facilities such as landfills. A large direct shear machine is used to carry out 90 geosynthetic interface tests. The test results show a strain softening behavior with a very small dilatancy (<0.5 mm) and nonlinear failure envelopes at a normal stress range of 25-450 kPa. The influences of the micro-level structure of these geosynthetics on the macro-level interface shear behavior are discussed in detail. This study has generated several practical recommendations to help professionals to choose what materials are more adequate. From the three geotextiles tested, the thermally bonded monofilament exhibits the best interface shear strength under high normal stress. For low normal stress, however, needle-punched monofilaments are recommended. For the regular textured geomembranes tested, the space between the asperities is an important factor. The closer these asperities are, the better the result achieves. For the irregular textured geomembranes tested, the nonwoven geotextiles made of monofilaments produce the largest interface shear strength

Modelado y verificación de sistemas digitales con SystemVerilog

El objetivo principal de este proyecto es presentar la metodología de modelado y verificación con SystemVerilog, un lenguaje para la descripción y verificación de sistemas digitales (Hardware Description and Verification Language). La explicación de la aplicación del lenguaje está orientada a diseñadores con conocimientos de modelado VHDL. En primer lugar se describe el modelado de sistemas digitales con SystemVerilog. Se exponen las técnicas para modelar el funcionamiento de circuitos combinacionales, circuitos secuenciales y circuitos complejos. Después se explica la realización de bancos de test SystemVerilog para verificar el correcto funcionamiento de los modelos. A continuación se describe el lenguaje de especificación de propiedades de SystemVerilog (SVA, SystemVerilog Assertions), explicando la formulación de propiedades temporales y el uso de aserciones, mostrando ejemplos y un caso de aplicación sencillo. Para ilustrar la aplicación del modelado SystemVerilog se realiza el modelo de un master I2C, con el que se construye un circuito de medida de temperatura y humedad que se materializa en hardware con la tarjeta de prototipado DECA MAX10, que dispone de un sensor de temperatura y humedad (HDC1000, de Texas Instruments), y una tarjeta de expansión, XDECA, que se emplea para presentar las medidas. Abstract: The purpose of the present project is to introduce a Hardware Description Language called SystemVerilog, starting from some knowledge of VHDL language. The realization of the project consisted, first, in the study of the elements of SystemVerilog that are dedicate to model digital systems and the part which concerns the specification of temporary properties. On the first chapters of the present project, is going to be explained how to model and implement combinational logic and sequential circuits. In addition, how to verify this circuits using Test-Bench. Throughout the document is being described how to implement an application that measures through a temperature and humidity sensor (HDC1000, from Texas instruments). To develop the application it has been used the DECA prototype board, that includes the sensor with an I2C interface, and the XDECA expansion board. Furthermore, before describing how to implement the application, is going to be described the SystemVerilog Property Specification Language (SVA, SystemVerilog Assertions). This section explains the temporary properties and the use of assertions with a simple application example. To summarize, the project have two different sections, the first one is more a theoretical part that include the most important concepts to learn about how to implement the language SystemVerilog. The second part will develop the simulation and verification of the application. In our case, to do the verification of the measurement application, it will be used a tool called Quartus II

Modelado y verificación de sistemas digitales con SystemVerilog

El objetivo principal de este proyecto es presentar la metodología de modelado y verificación con SystemVerilog, un lenguaje para la descripción y verificación de sistemas digitales (Hardware Description and Verification Language). La explicación de la aplicación del lenguaje está orientada a diseñadores con conocimientos de modelado VHDL. En primer lugar se describe el modelado de sistemas digitales con SystemVerilog. Se exponen las técnicas para modelar el funcionamiento de circuitos combinacionales, circuitos secuenciales y circuitos complejos. Después se explica la realización de bancos de test SystemVerilog para verificar el correcto funcionamiento de los modelos. A continuación se describe el lenguaje de especificación de propiedades de SystemVerilog (SVA, SystemVerilog Assertions), explicando la formulación de propiedades temporales y el uso de aserciones, mostrando ejemplos y un caso de aplicación sencillo. Para ilustrar la aplicación del modelado SystemVerilog se realiza el modelo de un master I2C, con el que se construye un circuito de medida de temperatura y humedad que se materializa en hardware con la tarjeta de prototipado DECA MAX10, que dispone de un sensor de temperatura y humedad (HDC1000, de Texas Instruments), y una tarjeta de expansión, XDECA, que se emplea para presentar las medidas. Abstract: The purpose of the present project is to introduce a Hardware Description Language called SystemVerilog, starting from some knowledge of VHDL language. The realization of the project consisted, first, in the study of the elements of SystemVerilog that are dedicate to model digital systems and the part which concerns the specification of temporary properties. On the first chapters of the present project, is going to be explained how to model and implement combinational logic and sequential circuits. In addition, how to verify this circuits using Test-Bench. Throughout the document is being described how to implement an application that measures through a temperature and humidity sensor (HDC1000, from Texas instruments). To develop the application it has been used the DECA prototype board, that includes the sensor with an I2C interface, and the XDECA expansion board. Furthermore, before describing how to implement the application, is going to be described the SystemVerilog Property Specification Language (SVA, SystemVerilog Assertions). This section explains the temporary properties and the use of assertions with a simple application example. To summarize, the project have two different sections, the first one is more a theoretical part that include the most important concepts to learn about how to implement the language SystemVerilog. The second part will develop the simulation and verification of the application. In our case, to do the verification of the measurement application, it will be used a tool called Quartus II

Estudio médico legal del suicidio en España en el periodo 2000-2012

Regarding the suicide as a cause of death, in this study we start from the assumption that the number os suicides in the XXI century in Spain has changed trough time and considering the age, sex and method used. Having gotten the results from the national statistics institute, we have proved that our hypothesis was correct, observing firstly a higher prevalence among men than women. Regarding the age, the most common group to comit suicide are those between 30 and 40 years old, with little variation over time. Comparing the different methods that are used, we see a predominance of hanging among men, and jumping from a high spot among women, being the other methods far less common. If we study the variation through time of the suicide in general, we may observe an increase from 2005, becoming unwavering, with little variation, from this date.Estudiando el suicidio como causa de muerte, en este estudio partimos de la hipótesis de que el número de suicidios en España en el siglo XXI ha variado en el tiempo, con respecto a la edad, sexo y métodos utilizados. Obteniendo los datos estadísticos del Instituto Nacional de Estadística, hemos comprobado que nuestra hipótesis era cierta, observándose en primer lugar mayor prevalencia entre los hombres que entre las mujeres. Con respecto a la edad, la década más habitual para los suicidios consumados es entre los 30 y 40 años, con poca variación a lo largo de los años. Al comparar los métodos utilizados, observamos un predominio del ahorcamiento entre los hombres y de precipitación al vacío por parte de las mujeres, quedando el resto de métodos por detrás. Si tenemos en cuenta la variación a lo largo del periodo estudiado en términos globales, podemos hablar de un notable aumento a partir del año 2005 con respecto a los anteriores, manteniéndose constante, con ligeras variaciones, a partir de dicho año