A Radiation hard bandgap reference circuit in a standard 0.13um CMOS Technology

With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increased radiation tolerance of MOS transistors. Combined with special layout techniques, this yields circuits with a high inherent robustness against X-rays and other ionizing radiation. In bandgap voltage references, the dominant radiation-susceptibility is then no longer associated with the MOS transistors, but is dominated by the diodes. This paper gives an analysis of radiation effects in both MOSdevices and diodes and presents a solution to realize a radiation-hard voltage reference circuit in a standard CMOS technology. A demonstrator circuit was implemented in a standard 0.13 m CMOS technology. Measurements show correct operation with supply voltages in the range from 1.4 V down to 0.85 V, a reference voltage of 405 mV 7.5 mV ( = 6mVchip-to-chip statistical spread), and a reference voltage shift of only 1.5 mV (around 0.8%) under irradiation up to 44 Mrad (Si)

Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector design goals, the design of the chip and the first experimental results

Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise

Low power discriminator for ATLAS pixel chip

The design of the front-end (FE) pixel electronics requires low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is largely reduced allowing the material reduction in the B-layer

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fVCO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160 Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers