Kluit, R

Schipper, J D

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Low Noise Amplifier for Capacitive Detectors.J. D. SchipperR KluitNIKHEF, Kruislaan 4091098SJ Amsterdam, Netherlandsjds@nikhef.nlAbstractAs a design study for the LHC experiments a 'LowNoise Amplifier Shaper' for capacitive detectors is devel-oped. This amplifier is designed in 0.6 um CMOS tech-nology from AMS.The goal was to design an amplifier with a noise con-tribution of 250 electrons, and 12 electrons per pF contri-bution from the input capacitor and a relative high gain.A test chip with two versions of the amplifier, a 'radia-tion tolerant' (gate-around FET's) and a 'rectangular' ver-sion has been fabricated and is now under test.These designs, and there characteristics, simulated andmeasured, will be compared and discussed.I. INTRODUCTIONA other goal of this project was to get more experiencewith the design- tools, methods and technologies in ana-logue IC design.The pre-amplifier should have, besides the noise con-straints, a relative high gain and low power consumption.The amplifier should be able to withstand a certain ra-diation level. To study the influence of radiation, two ver-sions of the amplifier are designed. The versions are a‘rectangular’ and a ‘gate around’ (radiation tolerant) ver-sion. The basic difference in layout between these twoversions is shown in figure 1.gate leakage path Figure 1: A ‘rectangular’ FET and a ‘gate-around’ FETThe left FET in figure 1 is the 'rectangular' version, theright FET the ‘gate-around’ version. Radiation damagesespecially the N-type FET. It causes a leakage currentaround the end of the gate. The gate of a ‘gate-around’FET has no end, so no leakage current can occur. On thetest chip 4 channels of each version are realized.This document describes the behavior of the circuitswhen they are “biased for speed”. This means short timeconstants for the preamp and shaper, which results in un-dershoot at the shaper outputs.II.  THE PREAMPLIFIERThe amplifier is based on a single FET amplifier.In this circuit the gate of the FET M0 is the input andthe drain the output.Optimising the circuit for noise makes the input FETwide. Optimising for bandwidth however subscribes asmall FET, to reduce the Miller capacitance.M0M1M16M2M13M28M30C0Inpre_bias1pre_bias3VSSVSSGNDVSSVSSVDDGNDVSSpre_bias2pre_resVDDoutputFigure 2: The schematic diagram of the rectangular version.To optimise the circuit for gain and power a cascodecircuit is used. In this circuit the amplifying steps are sepa-rated. In a single FET amplifier the conversions ‘inputvoltage to drain current’, and ‘drain current to output volt-age’ are realized in just one FET. In a cascode schematicdiagram both conversions have their own FET, which canbe optimized for its purpose.Optimising the circuit for noise requires a wide-channel input FET. A narrow channel is better to reducethe Miller capacitance (larger bandwidth).A cascode circuit is the optimum for both require-ments. A folded cascode is used to implement this con-figuration within the power supply limits.A. ‘Rectangular’ amplifierThe amplifier is a charge amplifier, so the main feed-back is a capacitor. In figure 2 the schematic diagram of the pre-amplifierin the ‘rectangular version’ is drawn. The feedback resis-tor (FET M2) in parallel with the feedback capacitor isrequired to control the DC operating point of the amplifier.The output level of the amplifier will stabilize without anyprecautions on about –1 Volt. This would give an asym-metrical dynamic range. To make this symmetrical, theoutput level should stabilize at 0 Volt. To realize this, onegate-source voltage is subtracted from the output of theamplifier.The resistor is needed for DC and low frequency feed-back. The resistance is adjustable by an external voltage(pre_res) to control the trailing edge of the amplifier sig-nal. To operate the circuit, 3 DC bias currents must beapplied:1. input FET bias (pre_bias_1),2. cascode FET bias (pre_bias_2),3. subtraction network bias  (pre_bias_3).B. 'Gate around' amplifierM0M1putpre_bias1VDD VDDpre_respre_bias2VSS VSSVSSM16GNDM13VDDM2pre_bias3C0 VDD VDDVDDoutputVDDFigure 3: Schematic diagram of the gate around version.The circuit is quite similar to the previous version. Themajor change is due to the fact that we cannot use a N-FET as a feedback (in ‘gate around’ it is not possible tomake a FET longer then wide), so a P-FET is used instead.The operating voltage on the gate of the feedback FET,when changed from the N-type to the P-type, is below –2Volt, which is unacceptable. To get this voltage betweenthe power supplies we have to change two things (see fig-ure 2):1. Connect the source of M0 to VDD (+2 Volt). Thislifts the gate of FET M0 to +1 Volt.2. The level subtraction at the output must becomelevel adder. This makes the output again about 0Volt.III. THE SHAPERThis circuit has the same configuration as the circuit ofthe pre-amplifier. The differences between the circuits arethe input capacitor and the dimensions of the used compo-nents.A. 'Rectangular' shaperThe shaper is an active band-pass filter. The compo-nents that control the bandwidth of this filter are the inputcapacitor, the feedback capacitor and the feedback resis-tor. The feedback capacitor and resistor determine the highroll off point, while the input capacitor and the feedbackresistor control the low roll off point.inputC6M33GNDVDDsha_bias1M39VSSsha_resC10VSSM38sha_bias2M31VDDM37VSSGNDsha_bias3outputM34VSSM35VSSFigure 4: The schematic diagram of the shaper, ‘normal’ ver-sion.B. 'Gate around' shaper.The differences between the ‘rectangular’ and the ‘gatearound’ versions are similar as with the pre-amplifier ver-sions.inputC6sha_bias1VSS VSSM39M33VDD VDDsha_bias2sha_resVDDM38VDDC10M31M37VSSGNDsha_bias3VDD VDDVDDoutputFigure 5: The schematic diagram of the shaper, 'Gate Around'version.IV. THE OUTPUT BUFFERThe shaper signals are measured in the test set-up withan oscilloscope. The oscilloscope has high impedance in-puts (1M•), with a capacitive load of 10 pF. Because theshaper output is does not have the capability to drive acapacitive load, the signals need to be buffered.inputbiasoutputVDDVSSVSSVSSVSSVSSVSSVDDVDDVDDFigure 6: The schematic diagram of the output buffer.The buffer circuit is equal for both versions. The cir-cuit consists of a differential amplifier with a high currentoutput stage. The differential amplifier is designed to cre-ate a buffer with a gain of 1.V. THE CIRCUIT SIMULATIONSThe schematic diagrams above are the result of exten-sive list of simulations, in which we looked for the bestcombination of parameters.During the simulations, and also later during the meas-urement, we used an input charge of 1 MIP, which corre-sponds to ~12000 electrons in 150µm silicon. The chargeis injected via a capacitor of 1.5pF. The applied voltagestep is:mVpCQnCQU elel 28,151106021,112000 19    In figure 7 shows the simulated step response of theamplifier. The upper line is the response of the ‘rectangu-lar’ version and the lower line of the ‘gate around’ ver-sion. A capacitor of 20pF was connected at the input tosimulate the detector capacitance.The gain of both versions differs due to the differencesin the point of operation of the input FET (M0) in bothversions. The source is connected to GND or to VDD.Figure 7: The step response of the circuits.This simulation is done with a relatively fast settlingtime for the pre-amplifier. This results in a fast fallingedge of the output pulse on the pre-amplifier and 60%overshoot after the shaper. In case the amplifier is biasedfor a time constant, much longer than of the shaper, noundershoot will occur.The circuit is optimised for gain, speed and noise. Forfigure 7 a detector capacitance of 20pF was used.Figure 8 and 9 show the dependency of the gain andS/N in relation with the input capacitance (detector) of theamplifier and shaper.Also simulated is the dynamic range of the circuits.The result is plotted in figure 10 and 11, for an input rangeof –10 to +10 MIP.O u tp u t (m V )C a p ac ito r  (p F )01020304050607080901000 5 10 15 20 25 30Gate aroundRectangularFigure 8: Gain plot, simulatedN o is e  (e le c tro n s )C a p a c ito r  (p F )05 0 01 0 0 01 5 0 02 0 0 02 5 0 03 0 0 00 5 1 0 1 5 2 0 2 5 3 0G a te  a r o u n dR e c ta n g u la rFigure 9: Noise plot, simulated.O u tp u t (m V )In p u t ( M IP )-400-300-200-1000100200300400500-10 -8 -6 -4 -2 0 2 4 6 8 10RectangularreferenceerrorFigure 10: The dynamic range of the ‘rectangular’ version.O u tp u t (m V )In p u t (M IP )-800-600-400-2000200400600800-10 -8 -6 -4 -2 0 2 4 6 8 10Gate AroundreferenceerrorFigure 11: The dynamic range of the ‘gate around’ version.All simulations are done with the bias settings from ta-ble 1. In the measurements the same bias settings are used,to allow a good comparison between both results.Table 1: Settings used with the simulationCircuit Signal net rect GAPre-amplifier Ibias input FET Ipre_bias1 500 500 uAIbias cascode FET Ipre_bias2 -10 -50 uAIbias level shifter Ipre_bias2 1 -1 uAV feedback resistor Vpre_res 500 -500 mVShaper Ibias input FET Isha_bias1 10 20 uAIbias cascode FET Isha_bias2 -2 -4 uAIbias level shifter Isha_bias3 500 -1 nAV feedback resistor Vsha_res 500 -500 mVVdd +2 VVss -2 VVI. MEASUREMENTSThree measurements are made with the chip, gain, dy-namic range and noise.For the gain test the set-up in figure 12 is used. With adigital oscilloscope a large number of measurements aregathered and the mean of peak values gives the size of theoutput signal for 1 MIP.D .U .T . -2 0  d B -2 0  d B -2 0  d BFigure 12: The test set-up.O u tp u t  (m V )C a p a c ito r  (p F )01020304050600 5 10 15 20 25 30Gate aroundRectangularFigure 13: Gain plot, measured.O u tp u t (m V )In p u t (M IP )-250-200-150-100-50050100150200250-10 -8 -6 -4 -2 0 2 4 6 8 10RectangularreferenceerrorFigure 14: The measured dynamic range, ‘rectangular’ version. Output (mV) Input (MIP) -300 -200 -100 0 100 200 300 -10 -8 -6 -4 -2 0 2 4 6 8 10 Gate Around reference error Figure 15: The measured dynamic range, ‘gate around’ version.In the figures 15 and 16 the plots of the measured out-put signal is plotted over –10 to +10 MIP. Due to the lowgain bias setting, the full dynamic output range is notreached.For the noise test the input of the amplifier is left open,besides the detector capacitance. The oscilloscope calcu-lates the RMS value of the AC signal at the output (Fig-ure: 12). Similar to the simulations, the test is done with 7values for the detector capacitance.n o is e  (e le c tro n s )C a p a c ito r  (p F )0500100015002000250030003500400045000 5 10 15 20 25 30Gate aroundRectangularFigure 16: The noise plot, measured.Table 2: Comparing simulation and tests. M easured  Sim ulation  D elta 20 20 (pF) (pF) G ate  around: 35 50 0.7 N oise [mV ] 7.2 7.3 1.0 N oise [e l] 2469 1741 1.4 S /N 4.9 6.9 1.4 Rectangular: 20 28 0.7 N oise [mV ] 4.6 4.6 1.0 N oise [e l] 2760 1956 1.4 S /N 4.3 6.1 1.4 O utput 1M IP  [mV ] O utput 1M IP  [mV ] The measured bias currents and voltages show lessthen 8% deviation from the expected simulated values.Other differences are: Rectangular version:x The actual gain is less than simulated.x The value of the noise is the same, but due to lowergain is the S/N ratio lower than expected.x The linearity is acceptable between +/- 4MIP. Outsidethat the deviation goes up to 10%.Gate around version:x The actual gain is less than simulated.x The value of the noise is the same, but due to lowergain is the S/N ratio lower than expected.x The non-linearity shows the same behaviour, but thedeviation is worse.1.  CONCLUSIONSSince the preamp shows a slower 1st slope, the shaperoutput is less then expected. This also results in a worseS/N ratio than expected.The feedback FET’s has been designed to short, this incombination with a small Cfb (~25fF) results in an insta-ble operation point for the rectangular version for longer(>1us) time constants. These small components could bethe cause of the differences between simulation and meas-urement.In case the circuit is biased as presented (with shorttime constants) there is no instability but the S/N ratio ispoor.Measurements show a poor linearity, this also is adrawback of a short feedback transistor since the linearrange is rather small.VII. WORK TO BE DONEFor better understanding of the differences betweensimulation and measurements, more measurements will bedone. Longer time constant of the preamplifier will beused to investigate the noise contributions. First measure-ments show a drastic increase in S/N at peaking times >50ns, at a gain of more than 120mV/12000e.In order to study the influence of radiation on both ver-sions, a number of chips will be irradiated and comparedwith the not irradiated devices.VIII. REFERENCES1. A CMOS Mixed-Signal Readout Chip for the Microstrip Detectors of HERA-B. W. Fallot-Burghardt.2. Low-Noise Wide-Band Amplifiers in Bipolar andCMOS Technologies. Zhong Yuan Chang, W. M. C.Sansen.

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