Reconfigurable hybrid-switched-capacitor-resonant LED driver for multiple mains voltages

This paper presents a hybrid-switched-capacitor-resonant (HSCR) light-emitting diode (LED) driver based on a stackable switched-capacitor (SC) converter IC rated for 15-20-W applications. Bulky transformers have been replaced with an SC ladder to perform high-efficiency voltage step-down conversion; an LC-resonant output network provides almost lossless current regulation and demonstrates the potential of capacitive galvanic isolation. The integrated SC modules can be stacked in the voltage domain to handle a large range of input voltage ranges that largely exceed the voltage limitation of the medium-voltage-rated 120-V silicon technology. The LED driver demonstrates >91% efficiency over a rectified input dc voltage range from 160 to 180 Vdc with two stacked ICs; using a stack of four ICs >89.6% efficiency is demonstrated over an input range from 320 to 360 Vdc. The LED driver can dim its output power to around 10% of the rated power while maintaining >70% efficiency with a pulsewidth modulation-controlled clock gating circuit

Metacapacitors: Printed thin film, flexible capacitors for power conversion applications

The Metacapacitors project aims to improve efficiency, functionality and form factor of offline power converters suitable for LED solid-state lighting, with a view to developing an attractive technology platform for load management and power conversion across a broad range of applications. Based on integrated switched-capacitor (SC) topologies, the project adopts an integrated approach from materials to devices to circuits. We designed capacitors based on high-κ dielectric nanocrystals, that can be prepared using high-throughput microfabrication/ nanotechnology techniques, ink deposition and multilayering. The capacitor dielectric, a nanocomposite composed of (Ba, Sr)TiO3 nanocrystals in polyfurfuryl alcohol (BST/PFA, κ > 20, 100Hz-1 MHz, loss < 0.01, 20 kHz), targets a high volumetric capacitance density and ripple current capability. The Dielectric is demonstrated to function in a finished capacitor >1000 h at 125°C. The capacitors were board integrated with a custom hybrid-switched-capacitor-resonant dc-dc converter IC. The converter integrates a balanced SC front-end with a series resonant tank, enabling nearly lossless current regulation and tranformerless galvanic isolation. The converter IC can be stacked in the voltage domain to interface a range of inputs. The tested driver delivers about 15 Wat 470 mA to a string of 12 LEDs with 90% peak efficiency

Transistor analogs of emergent iono-neuronal dynamics

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications

The ATLAS experiment at the CERN Large Hadron Collider: a description of the detector configuration for Run 3

Abstract The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of  ℒ = 2 × 1034 cm-2 s-1 was routinely achieved at the start of fills, twice the design luminosity. For Run 3, accelerator improvements, notably luminosity levelling, allow sustained running at an instantaneous luminosity of  ℒ = 2 × 1034 cm-2 s-1, with an average of up to 60 interactions per bunch crossing. The ATLAS detector has been upgraded to recover Run 1 single-lepton trigger thresholds while operating comfortably under Run 3 sustained pileup conditions. A fourth pixel layer 3.3 cm from the beam axis was added before Run 2 to improve vertex reconstruction and b-tagging performance. New Liquid Argon Calorimeter digital trigger electronics, with corresponding upgrades to the Trigger and Data Acquisition system, take advantage of a factor of 10 finer granularity to improve triggering on electrons, photons, taus, and hadronic signatures through increased pileup rejection. The inner muon endcap wheels were replaced by New Small Wheels with Micromegas and small-strip Thin Gap Chamber detectors, providing both precision tracking and Level-1 Muon trigger functionality. Trigger coverage of the inner barrel muon layer near one endcap region was augmented with modules integrating new thin-gap resistive plate chambers and smaller-diameter drift-tube chambers. Tile Calorimeter scintillation counters were added to improve electron energy resolution and background rejection. Upgrades to Minimum Bias Trigger Scintillators and Forward Detectors improve luminosity monitoring and enable total proton-proton cross section, diffractive physics, and heavy ion measurements. These upgrades are all compatible with operation in the much harsher environment anticipated after the High-Luminosity upgrade of the LHC and are the first steps towards preparing ATLAS for the High-Luminosity upgrade of the LHC. This paper describes the Run 3 configuration of the ATLAS detector.</jats:p

The ATLAS experiment at the CERN Large Hadron Collider: a description of the detector configuration for Run 3

Abstract The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of  ℒ = 2 × 1034 cm-2 s-1 was routinely achieved at the start of fills, twice the design luminosity. For Run 3, accelerator improvements, notably luminosity levelling, allow sustained running at an instantaneous luminosity of  ℒ = 2 × 1034 cm-2 s-1, with an average of up to 60 interactions per bunch crossing. The ATLAS detector has been upgraded to recover Run 1 single-lepton trigger thresholds while operating comfortably under Run 3 sustained pileup conditions. A fourth pixel layer 3.3 cm from the beam axis was added before Run 2 to improve vertex reconstruction and b-tagging performance. New Liquid Argon Calorimeter digital trigger electronics, with corresponding upgrades to the Trigger and Data Acquisition system, take advantage of a factor of 10 finer granularity to improve triggering on electrons, photons, taus, and hadronic signatures through increased pileup rejection. The inner muon endcap wheels were replaced by New Small Wheels with Micromegas and small-strip Thin Gap Chamber detectors, providing both precision tracking and Level-1 Muon trigger functionality. Trigger coverage of the inner barrel muon layer near one endcap region was augmented with modules integrating new thin-gap resistive plate chambers and smaller-diameter drift-tube chambers. Tile Calorimeter scintillation counters were added to improve electron energy resolution and background rejection. Upgrades to Minimum Bias Trigger Scintillators and Forward Detectors improve luminosity monitoring and enable total proton-proton cross section, diffractive physics, and heavy ion measurements. These upgrades are all compatible with operation in the much harsher environment anticipated after the High-Luminosity upgrade of the LHC and are the first steps towards preparing ATLAS for the High-Luminosity upgrade of the LHC. This paper describes the Run 3 configuration of the ATLAS detector.</jats:p