Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (ISUB) and the band-to-band tunneling (BTBT) current (IBTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperatures (ranging from 25°C to 100°C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25°C and 100°C, respectively, on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop

Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects

With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the photolithography. Various reconfigurable architectures have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density systems consisting of nanometer-scale elements are likely to have many imperfections and variations; thus, defect-tolerance is considered as one of the most exigent challenges. In this paper, we evaluate three different logic mapping algorithms with defect avoidance to circumvent clustered defective crosspoints in nanowire reconfigurable crossbar architectures. The effectiveness of inherited redundancy and configurability utilization is demonstrated through extensive parametric simulations

Leakage Minimization Technique for Nanoscale CMOS VLSI

Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents

Accurate Macro-Modeling for Leakage Current for I\u3csub\u3eDDQ\u3c/sub\u3e Test

This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results

Photochemical Organonitrate Formation in Wet Aerosols

Water is the most abundant component of atmospheric fine aerosol. However, despite rapid progress, multiphase chemistry involving wet aerosols is still poorly understood. In this work, we report results from smog chamber photooxidation of glyoxal and OH &ndash; containing ammonium sulfate or sulfuric acid particles in the presence of NOx and O3 at high and low relative humidity. Particles were analyzed using ultra high performance liquid chromatography coupled to quadrupole time-of-flight mass spectrometry (UPLC-Q-TOF-MS). During the 3 hour irradiation, OH oxidation products of glyoxal that are also produced in dilute aqueous solutions (e.g., oxalic acids and tartaric acids) were formed in both ammonium sulfate (AS) aerosols and sulfuric acid (SA) aerosols. However, the major products were organonitrogens (CHNO), organosulfates (CHOS), and organonitrogen-sulfates (CHNOS). These were also the dominant products formed in the dark chamber indicating non-radical formation. In the humid chamber (> 70 % RH), two main products for both AS and SA aerosols were organonitrates, which appeared at m/z&minus; 147 and 226. They were formed in the aqueous phase via non-radical reactions of glyoxal and nitric acid, and their formation was enhanced by photochemistry because of the photochemical formation of nitric acid via reactions of peroxy radicals, NOx and OH during the irradiation.</html

Jitter Analysis of PWM Scheme in High Speed Serial Link

This paper presents a jitter analysis method for PWM (pulse width modulation) scheme in high-speed serial links. The data rate of PWM with N different pulse widths (PWM-N) scheme is (log2N) x (symbol rate). However it increases the timing jitter of the transmitted signal. The timing jitter is determined by the pulse widths of PWM symbols and the characteristics of the communication channel. The analysis of the first-order systems and the second-order systems demonstrates that data dependent jitter (DDJ) strongly depends on the -3dB frequency and the damping ratio of the systems. The proposed jitter analysis method makes it possible to determine the pulse width of PWM symbols with the known characteristics of the channel

Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach

Influence of HEMA content on the mechanical and bonding properties of experimental HEMA-added glass ionomer cements

The purpose of this study was to determine the influence of incrementally added uncured HEMA in experimental HEMA-added glass ionomer cement (HAGICs) on the mechanical and shear bond strength (SBS) of these materials. Increasing contents of uncured HEMA (10-50 wt.%) were added to a commercial glass ionomer cement liquid (Fuji II, GC, Japan), and the compressive and diametral tensile strengths of the resulting HAGICs were measured. The SBS to non-precious alloy, precious alloy, enamel and dentin was also determined after these surfaces were subjected to either airborne-particle abrasion (Aa) or SiC abrasive paper grinding (Sp). Both strength properties of the HAGICs first increased and then decreased as the HEMA content increased, with a maximum value obtained when the HEMA content was 20% for the compressive strength and 40% for the tensile strength. The SBS was influenced by the HEMA content, the surface treatment, and the type of bonding surface (

Chronological Notes on Byzantine Documents II

Recently, we proposed a new clock-free nanowire crossbar architecture based on a delayinsensitive paradigm called Null Convention Logic (NCL). The proposed architecture has simple periodic structure that is suitable for non-deterministic nanoscale assembly and does not require a clock distribution network - so it is intrinsically free from timing-related failure modes. Even though the proposed architecture offers improved manufacturability, it is still not free from defects. This paper elaborates on the different programming techniques to map a given threshold gate macro on a random PGMB (Programmable Gate Macro Block) with predefined dimension. Defect-Aware and Defect Unaware approaches have been considered to map a given threshold gate onto a PGMB without affecting its functionality. Defect aware approach uses a defect map, gate table which help in efficient programming and also conservative use of resources. Defect unaware approach on the other hand is faster than defect aware approach, does not use defect maps and is not as efficient as defect aware approach. Parametric simulation results using MATLAB are used to show the programmability of these approaches under various circumstances