Improved effective mobility extraction in MOSFETs

The standard method of extracting carrier effective mobility from electrical measurements on MOSFETs is reviewed and the assumptions implicit in this method are discussed. A novel technique is suggested that corrects for the difference in drain bias during IV and CV measurements. It is further shown that the lateral field and diffusion corrections, which are both commonly neglected, in fact cancel. The effectiveness of the proposed technique is demonstrated by application to data measured on a quasi-planar SOI finFET at 300 K and 4 K

High-field current transport and charge trapping in buried oxide of SOI materials under high-field electron injection, Journal of Telecommunications and Information Technology, 2004, nr 1

Mechanisms of the charge transfer, the charge trapping, and the generation of positive charge during the high-field electron injection into buried oxide of silicon-on-insulator structures fabricated by different technologies are analyzed based on the data obtained from current-voltage, injection current-time, and capacitance-voltage characteristics together with SIMS data. Electron injection both from the Si film and the Si substrate is considered. The possibility of using the trap-assisted electron tunneling mechanisms to explain the high-field charge transfer through the buried oxides of UNIBOND and SIMOX SOI materials is considered. It is shown that considerable positive charge is accumulated near the buried oxide/substrate interface independently from the direction of the injection (from the lm or from the silicon substrate) for UNIBOND and SIMOX SOI structures. Thermal stability of the charge trapped in the buried oxides is studied at temperatures ranging from 20 to 400C. The theory is compared with the experimental data to find out the mechanisms of the generation of positive charge in UNIBOND and SIMOX buried oxides

Design and fabrication of silicon-on-silicon-carbide substrates and power devices for space applications

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to silicon carbide (SiC). This novel silicon-on-silicon-carbide (Si/SiC) substrate solution promises to combine the benefits of silicon-on-insulator (SOI) technology (i.e device confinement, radiation tolerance, high and low temperature performance) with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance). Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions

High-temperature instability processes in SOI structures and MOSFETs, Journal of Telecommunications and Information Technology, 2001, nr 1

The paper reviews the problems related to BOX high-temperature instability in SOI structures and MOSFETs. The methods of bias-temperature research applied to SOI structures and SOI MOSFETs are analysed and the results of combined electrical studies of ZMR, and SIMOX SOI structures are presented. The studies are focused mainly on electrical discharging processes in the BOX at high temperature and its link with new instability phenomena such as high-temperature kink effects in SOI MOSFETs

Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs

The charge coupling between the gate and substrate is a fundamental property of any fully-depleted silicon-on-insulator (SOI) MOS transistor, which manifests itself as a dependence of electrical characteristics at one Si film/dielectric interface on charges at the opposite interface and opposite gate bias. Traditionally, gate-to-substrate coupling in SOI MOS transistors is described by the classical Lim-Fossum model. However, in the case of SOI MOS transistors with ultra-thin silicon bodies, significant deviations from this model are observed. In this paper, the behavior of gate coupling in SOI MOS structures with ultra-thin silicon films and ultra-thin gate dielectrics is studied and analyzed using experimental data and one-dimensional numerical simulations in classical and quantum-mechanical modes. It is shown that in these advanced transistor structures, coupling characteristics (dependences of the front- and back-gate threshold voltages on the opposite gate bias) feature a larger slope and much wider (more than doubled) linear region than that predicted by the Lim-Fossum model. These differences originate from both electrostatic and quantization effects. A simple analytical model taking into account these effects and being in good agreement with numerical simulations and experimental results is proposed

The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer

Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities, Journal of Telecommunications and Information Technology, 2007, nr 3

The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained

Influence of free radical surface activation on Si/SiC heterogeneous integration by direct wafer bonding

In this study, a surface activated bonding method using remote plasma is applied to realize the direct wafer bonding of Si and SiC. A comparison of different surface treatments is reported. Hydrophilic and hydrophobic wafers have been exposed to in-situ argon and nitrogen radicals generated by remote plasma for surface activation before bonding. A comparison of the bonding yield and surface condition has been conducted and analyzed as a function of the surface treatments. It has been shown that N2 plasma leads to the highest yield of > 97 %, strongest bond of > 360 N and interfacial layer (IL) thickness of ~1.5 nm