Synchronization methods for the PAC RPC trigger system in the CMS experiment

The PAC (pattern comparator) is a dedicated muon trigger for the CMS (Compact Muon Solenoid) experiment at the LHC (Large Hadron Collider). The PAC trigger processes signals provided by RPC (resistive plate chambers), a part of the CMS muon system. The goal of the PAC RPC trigger is to identify muons, measure their transverse momenta and select the best muon candidates for each proton bunch collision occurring every 25 ns. To perform this task it is necessary to deliver the information concerning each bunch crossing from many RPC chambers to the trigger logic at the same moment. Since the CMS detector is large (the muon hits are spread over 40 ns), and the data are transmitted through thousands of channels, special techniques are needed to assure proper synchronization of the data. In this paper methods developed for the RPC signal synchronization and synchronous transmission are presented. The methods were tested during the MTCC (magnet test and cosmic challenge). The performance of the synchronization methods is illustrated by the results of the tests

Performance of the CMS muon trigger system in proton-proton collisions at √s = 13 TeV

The muon trigger system of the CMS experiment uses a combination of hardware and software to identify events containing a muon. During Run 2 (covering 2015-2018) the LHC achieved instantaneous luminosities as high as 2 × 10 cm s while delivering proton-proton collisions at √s = 13 TeV. The challenge for the trigger system of the CMS experiment is to reduce the registered event rate from about 40 MHz to about 1 kHz. Significant improvements important for the success of the CMS physics program have been made to the muon trigger system via improved muon reconstruction and identification algorithms since the end of Run 1 and throughout the Run 2 data-taking period. The new algorithms maintain the acceptance of the muon triggers at the same or even lower rate throughout the data-taking period despite the increasing number of additional proton-proton interactions in each LHC bunch crossing. In this paper, the algorithms used in 2015 and 2016 and their improvements throughout 2017 and 2018 are described. Measurements of the CMS muon trigger performance for this data-taking period are presented, including efficiencies, transverse momentum resolution, trigger rates, and the purity of the selected muon sample. This paper focuses on the single- and double-muon triggers with the lowest sustainable transverse momentum thresholds used by CMS. The efficiency is measured in a transverse momentum range from 8 to several hundred GeV

Modular & reconfigurable common PCB-platform of FPGA based LLRF control system for TESLA Test Facility

The paper includes a description of predicted functionalities to be implemented in a universal motherboard (MB) for the next generation of LLRF control system for TESLA. The motherboard bases on a number of quasi-autonomous embedded executive modules. The modules are implemented in a few FPGA chips featured by the MB. The paper presents a practical design of the MB. The initial (basic) solution of the MB has the Cyclone as the chip where the board management is embedded. The board features communication modules – VME and micro, single chip PC with Ethernet. The board provides power supply for the FPGA chips. The board has fast internal communication between particular modules

Parameterized control layer of FPGA based cavity controller and simulator for TESLA Test Facility

The paper describes a functional idea of the parameterized control layer for the FPGA based advanced electronic and photonic systems. The systems under considerations are used (or planned to be used) for the construction of distributed, control, simulation, measurement and data acquisition in the Low Level Radio Frequency (LLRF) part of the TESLA and X-Ray FEL projects in DESY. Practical realization of the control layer was presented. The implementation was done in FPGA Xilinx VirtexII V3000 chip embedded in XtremeDSP Development Kit board by Nallatech. The designed and implemented communications protocol was described. The protocol is based on the standard parallel EPP transmission from the PC

TESLA Report 2003-30 Parameterized control layer of FPGA based cavity controller and simulator for TESLA Test Facility

The paper describes a functional idea of the parameterized control layer for the FPGA based advanced electronic and photonic systems. The systems under considerations are used (or planned to be used) for the construction of distributed, control, simulation, measurement and data acquisition in the Low Level Radio Frequency (LLRF) part of the TESLA and X-Ray FEL projects in DESY. Practical realization of the control layer was presented. The implementation was done in FPGA Xilinx VirtexII V3000 chip embedded in XtremeDSP Development Kit board by Nallatech. The designed and implemented communications protocol was described. The protocol is based on the standard parallel EPP transmission from the PC