Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors

A physics-based model for the surface potential and drain current for monolayer transition metal dichalcogenide (TMD) field-effect transistor (FET) is presented. Taking into account the 2D density-of-states of the atomic layer thick TMD and its impact on the quantum capacitance, a model for the surface potential is presented. Next, considering a drift-diffusion mechanism for the carrier transport along the monolayer TMD, an explicit expression for the drain current has been derived. The model has been benchmarked with a measured prototype transistor. Based on the proposed model, the device design window targeting low-power applications is discussed.Comment: 10 pages, 3 figure

Multi-domain ferroelectricity as a limiting factor for voltage amplification in ferroelectric field-effect transistors

We revise the possibility of having an amplified surface potential in ferroelectric field-effect transistors pointed out by [S. Salahuddin and S. Datta, Nano Lett. 8, 405 (2008)]. We show that the negative-capacitance regime that allows for such an amplification is actually bounded by the appearance of multi-domain ferroelectricity. This imposes a severe limit to the maximum step-up of the surface potential obtainable in the device. We indicate new device design rules taking into account this scenario.Comment: 4 pages, 3 figure

Steganalytic Methods for the Detection of Histogram Shifting Data Hiding Schemes

Peer-reviewedIn this paper, several steganalytic techniques designed to detect the existence of hidden messages using histogram shifting schemes are presented. Firstly, three techniques to identify specific histogram shifting data hiding schemes, based on detectable visible alterations on the histogram or abnormal statistical distributions, are suggested. Afterwards, a general technique capable of detecting all the analyzed histogram shifting data hiding methods is suggested. This technique is based on the effect of histogram shifting methods on the ¿volatility¿ of the histogram of the difference image. The different behavior of volatility whenever new data are hidden makes it possible to identify stego and cover images

High capacity audio watermarking using FFT amplitude interpolation

An audio watermarking technique in the frequency domain which takes advantage of interpolation is proposed. Interpolated FFT samples are used to generate imperceptible marks. The experimental results show that the suggested method has very high capacity (about 3kbps), without significant perceptual distortion (ODG about -0.5) and provides robustness against common audio signal processing such as echo, add noise, filtering, resampling and MPEG compression (MP3). Depending on the specific application, the tuning parameters could be selected adaptively to achieve even more capacity and better transparency

Robust high-capacity audio watermarking based on FFT amplitude modification

This paper proposes a novel robust audio watermarking algorithm to embed data and extract it in a bit-exact manner based on changing the magnitudes of the FFT spectrum. The key point is selecting a frequency band for embedding based on the comparison between the original and the MP3 compressed/decompressed signal and on a suitable scaling factor. The experimental results show that the method has a very high capacity (about 5 kbps), without significant perceptual distortion (ODG about -0.25) and provides robustness against common audio signal processing such as added noise, filtering and MPEG compression (MP3). Furthermore, the proposed method has a larger capacity (number of embedded bits to number of host bits rate) than recent image data hiding methods

The role of the Fermi level pinning in gate tunable graphene-semiconductor junctions

Graphene based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to 10⁵. Such a large number is likely due to the realization of an ultra clean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics based model of the gate tunable GS heterostructure where non-idealities such as Fermi Level Pinning (FLP) and a "bias dependent barrier lowering effect" has been considered. Using the model we have made a comprehensive study of the barristor's expected digital performance