The role of urban greenspace in children’s reward and punishment sensitivity

According to Life History Theory, environments with abundant and reliable resources encourage ‘slow’ (deliberative) strategies that are low-risk and focused on long-term outcomes. Arguably, greener neighbourhoods may approximate such environments, especially in urban settings. This study used the UK’s Millennium Cohort Study to investigate the role of greenness of the child’s immediate residential area at ages 9 months and 3, 5, 7, and 11 years in reward and punishment sensitivity, measured using the Cambridge Gambling Task (CGT), at age 11 years. Our sample was the children who lived in urban areas at all five time-points and with data on the CGT at the fifth (n = 5,012). Consistent with Life History Theory, we found that children in the least green areas were more likely to engage in ‘fast’ decision strategies than other children: they showed higher sensitivity to reward (or lower sensitivity to punishment). This association was robust to adjustment for confounders

Single Spin Asymmetry in Lepton Angular Distribution of Drell-Yan Processes

We study the single spin asymmetry in the lepton angular distribution of Drell-Yan processes in the frame work of collinear factorization. The asymmetry has been studied in the past and different results have been obtained. In our study we take an approach different than that used in the existing study. We explicitly calculate the transverse-spin dependent part of the differential cross-section with suitable parton states. Because the spin is transverse, one has to take multi-parton states for the purpose. Our result agrees with one of the existing results. A possible reason for the disagreement with others is discussed.Comment: Typos corrected. Conclusions unchange

Fidelity of SNP array genotyping using Epstein Barr virus-transformed B-lymphocyte cell lines: Implications for genome-wide association studies

Background: As availability of primary cells can be limited for genetic studies of human disease, lymphoblastoid cell lines (LCL) are common sources of genomic DNA. LCL are created in a transformation process that entails in vitro infection of human B-lymphocytes with the Epstein-Barr Virus (EBV). Methodology/Principal Findings: To test for genotypic errors potentially induced by the Epstein-Barr Virus transformation process, we compared single nucleotide polymorphism (SNP) genotype calls in peripheral blood mononuclear cells (PBMC) and LCL from the same individuals. The average mismatch rate across 19 comparisons was 0.12% for SNPs with a population call rate of at least 95%, and 0.03% at SNPs with a call rate of at least 99%. Mismatch rates were not correlated across genotype subarrays run on all sample pairs. Conclusions/Significance: Genotypic discrepancies found in PBMC and LCL pairs were not significantly different than control pairs, and were not correlated across subarrays. These results suggest that mismatch rates are minimal with stringent quality control, and that most genotypic discrepancies are due to technical artifacts rather than the EBV transformation process. Thus, LCL likely constitute a reliable DNA source for host genotype analysis. © 2009 Herbeck et al

The Economics of the Public Option: Evidence from Local Pharmaceutical Markets

We study the effects of competition by state-owned firms, leveraging the decentralized entry of public pharmacies to local markets in Chile. Public pharmacies sell the same drugs at a third of private pharmacy prices, because of stronger upstream bargaining and market power in the private sector, but are of lower quality. Public pharmacies induced market segmentation and price increases in the private sector, which benefited the switchers to the public option but harmed the stayers. The countrywide entry of public pharmacies would reduce yearly consumer drug expenditure by 1.6 percent

Impacts of Ti content and annealing temperature on electrical properties of Si MOS capacitors with HfTiON gate dielectric

Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits, 2009, p. 221-224HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N 2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds -1.75, increase of the gate capacitance becomes small. Surface roughness of the samples annealed at different temperatures is analyzed by AFM, and results show that high annealing temperature (e.g. 700 °C for 30 s) can produce smooth surface, thus resulting in low gate leakage current. ©2009 IEEE.published_or_final_versio

A novel MONOS memory with high-κ HfLaON as charge-storage layer

MIS capacitors with a high-κ HfLaON or HfLaO gate dielectric are fabricated by using a reactive sputtering method to investigate the applicability of the films as a novel charge-storage layer in a metaloxidenitrideoxidesilicon nonvolatile memory device. Experimental results indicate that the MIS capacitor with a HfLaON gate dielectric exhibits a large memory window, high program/erase speed, excellent endurance property, and reasonable retention. The involved mechanisms for these promising characteristics with HfLaON are thought to be in part from nitrogen incorporation leading to higher density of traps with deeper levels and, thus, higher trapping efficiency, stronger HfN and LaN bonds, and more stable atomic structure and HfLaONSiO 2 interface, as compared to the HfLaO dielectric. © 2011 IEEE.published_or_final_versio

Electrical properties of HfTiON gate-dielectric metal-oxide-semiconductor capacitors with different Si-surface nitridations

Electrical properties of HfTiON gate-dielectric metal-oxide-semiconductor (MOS) capacitors with different Si-surface nitridations in N2 O, NO, and N H3 prior to high- k film deposition are investigated and compared. It is found that the NO-nitrided sample exhibits low interface-state density and gate leakage current, and high reliability. This is attributed to formation of a SiON interlayer with suitable proportions of N and O. The MOS capacitor with Hf0.4 Ti0.6 Ox Ny SiON gate dielectric stack (capacitance equivalent thickness of 1.52 nm and k value of 18.9) prepared by NO surface nitridation has an interface-state density of 1.22× 1011 cm-2 eV-1 and gate leakage current density of 6× 10-4 A cm-2 (Vg =1 V). Moreover, only a small degradation of electrical properties after a stressing at 10 MVcm for 3000 s is observed for the NO-nitrided sample. © 2007 American Institute of Physics.published_or_final_versio

Improved electrical properties of metal-oxide-semiconductor capacitor with HfTiON gate dielectric by using HfSiON interlayer

Metal-oxide-semiconductor (MOS) capacitor with HfTiONHfSiON stack structure as high- k gate dielectric is fabricated, and its electrical properties are compared with those of a similar device with HfTiON only as gate dielectric. Experimental results show that the device with HfTiONHfSiON gate dielectric exhibits better interface properties, lower gate leakage current, and enhanced high-field reliability. All these improvements should be attributed to the fact that the HfSiON buffer layer effectively blocks the diffusion of Ti atoms to the Si substrate, thus resulting in a Si O2 Si -like HfSiONSi interface. © 2007 American Institute of Physics.published_or_final_versio

A compact threshold-voltage model of MOSFETs with stack high-k gate dielectric

In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interiayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interiayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current. ©2009 IEEE.published_or_final_versionThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009), Xian, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 236-23