Atomic Layer Deposition Josephson Junctions for Cryogenic Circuit Applications

Superconducting-insulating-superconducting (SIS) trilayers have been produced for Josephson Junction fabrication by thermal atomic layer deposition (ALD) processes. The trilayers are composed of alternating layers of Ti0.4N0.6/Al2O3/ Ti0.4N0.6, deposited at 450C, in a thermal ALD reactor on Al2O3-coated silicon. The conformal nature of the ALD process provides excellent step coverage of superconducting and insulating films. The film thickness of a single ALD cycle being one mono-layer, allows us to precisely control the tunnel-barrier insulator thickness by counting the number of ALD cycles during the insulator deposition step. Tunnel-junctions with critical current 500 A/cm2 are reported. Fabrication of Josephson Junctions and progress toward development of a single-element ALD Superconducting Quantum Interference Device (SQUID) will be discusse

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices

Cryogenic Detector Technology for Space Science Application

We review the current status of detector development at NASA's Goddard Space Flight Center and address future prospect for space science application. In particular, the IR detector capability and applicability to second generation SOFIA instrument will be discussed. We will examine areas such as 3-dimensional hybridization of large format bolometer arrays to readout multiplexers; advanced light coupling scheme for planar ortho-mode transducer circuitry; integration of high density readout wiring for low temperature detector arrays; and microwave multiplexers for large format superconducting detector arrays

Reconfigurable Microwave Phase Delay Element for Frequency Reference and Phase-Shifter Applications

A technique was developed to provide a reconfigurable high-precision micro - wave electrical phase delay for resonators and phase shifters. The invention employs multiple branches of transmission lines with open-ended or ground-ended terminations as configurable bits or digits. This technique minimizes the errors due to limited precision of switching devices. In addition, the proposed linear analytical approach significantly produces a much simpler design than that of other prior inventions at the time of this reporting. Microwave components such as filters, phase delay elements, or resonators require a method that can accurately adjust their frequency responses. Most tuning techniques offer very wide frequency tuning range; however, it is often difficult and expensive to tune their response in a very narrow operating frequency, especially when the tuning element reaches its minimum discrete step due to fabrication tolerances. The problem becomes worse as the operating frequency is in mm-wave frequency range (>26 GHz). The electrical tuning sensitivity of a microwave line is dependent on the position of the tuning element with respect to the reference termination. By placing this tuning element away from this reference with the main transmission line connecting the two elements together the sensitivity of the tuning element can change significantly. This concept can be used in the system that requires multiple tuning sensitivities. In this case, multiple tuning branches are superimposed in the main transmission line. The proposed invention allows the transmission-line electrical length to be accurately programmed using switching elements that have limited accuracy. The invention consists of multiple branches of transmission lines connected to discrete switching devices with open-ended terminations. They are used as discrete tuning elements. These elements are connected to the main microwave transmission line and are separated by a well-defined electrical degree spacing. Each branch is programmed to have different electrical degree sensitivity, such as a combination of discrete steps in each branch, which results in a reflective line with a unique effective phase response. To reduce the number of switching devices, it is desirable to program the devices in binary configuration where each branch represents one bit in the base-2 number system. This invention allows the transmission line electrical length to be tuned precisely with customizable sensitivity based on the known sensitivity of the base tuning circuit. The tuning resolution is dependent on the distance among tuning branches

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit patbs by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabric.ted parts were hybridized using a Suss FCI50 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available

Enabling Large Focal Plane Arrays through Mosaic Hybridization

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated

SHARC II: a Caltech Submillimeter Observatory facility camera with 384 pixels

SHARC II is a background-limited 350 μm and 450 μm facility camera for the Caltech Submillimeter Observatory undergoing commissioning in 2002. The key component of SHARC II is a 12×32 array of doped silicon 'pop-up' bolometers developed at NASA/Goddard. Each 1 mm × 1 mm pixel is coated with a 400 Ω/square bismuth film and located λ/4 above a reflective backshort to achieve >75% absorption efficiency. The pixels cover the focal plane with >90% filling factor. At 350 μm, the SHARC II pixels are separated by 0.65 λ/D. In contrast to the silicon bolometers in the predecessor of SHARC II, each doped thermistor occupies nearly the full area of the pixel, which lowers the 1/f knee of the detector noise to <0.03 Hz, under load, at the bath temperature of 0.36 K. The bolometers are AC-biased and read in 'total power' mode to take advantage of the improved stability. Each bolometer is biased through a custom ~130 MΩ CrSi load resistor at 7 K and read with a commercial JFET at 120 K. The JFETs and load resistors are integrated with the detectors into a single assembly to minimize microphonic noise. Electrical connection across the 0.36 K to 4 K and 4 K to 120 K temperature interfaces is accomplished with lithographed metal wires on dielectric substrates. In the best 25% of winter nights on Mauna Kea, SHARC II is expected to have an NEFD at 350 μm of 1 Jy Hz-1/2 or better. The new camera should be at least 4 times faster at detecting known point sources and 30 times faster at mapping large areas compared to the prior instrument

The Primordial Inflation Polarization Explorer (PIPER)

The Primordial Inflation Polarization Explorer (PIPER) is a balloon-borne cosmic microwave background (CMB) polarimeter designed to search for evidence of inflation by measuring the large-angular scale CMB polarization signal. BICEP2 recently reported a detection of B-mode power corresponding to the tensor-to-scalar ratio r = 0.2 on ~2 degree scales. If the BICEP2 signal is caused by inflationary gravitational waves (IGWs), then there should be a corresponding increase in B-mode power on angular scales larger than 18 degrees. PIPER is currently the only suborbital instrument capable of fully testing and extending the BICEP2 results by measuring the B-mode power spectrum on angular scales $\theta$ = ~0.6 deg to 90 deg, covering both the reionization bump and recombination peak, with sensitivity to measure the tensor-to-scalar ratio down to r = 0.007, and four frequency bands to distinguish foregrounds. PIPER will accomplish this by mapping 85% of the sky in four frequency bands (200, 270, 350, 600 GHz) over a series of 8 conventional balloon flights from the northern and southern hemispheres. The instrument has background-limited sensitivity provided by fully cryogenic (1.5 K) optics focusing the sky signal onto four 32x40-pixel arrays of time-domain multiplexed Transition-Edge Sensor (TES) bolometers held at 140 mK. Polarization sensitivity and systematic control are provided by front-end Variable-delay Polarization Modulators (VPMs), which rapidly modulate only the polarized sky signal at 3 Hz and allow PIPER to instantaneously measure the full Stokes vector (I, Q, U, V) for each pointing. We describe the PIPER instrument and progress towards its first flight.Comment: 11 pages, 7 figures. To be published in Proceedings of SPIE Volume 9153. Presented at SPIE Astronomical Telescopes + Instrumentation 2014, conference 915