Design of an Embedded Low Complexity Image Coder using CAL language

International audienceThe increasing complexity of image codecs and the time to market requires a high level design. Caltrop Actor Language (CAL) is a domain-specific language that provides useful abstractions for dataflow programming with actor. It has been chosen by the ISO/IEC standardization organization in the new MPEG standard called Reconfigurable Video Coding. This framework is adopted to design a multitude of codecs by combining actors. We present in this paper the specification and synthesis of the image coder LAR (Locally adaptive resolution) using the CAL framework. An HDL description and generation tools are used. The results show that such a high level design is possible. The quality of the resulting decoder implementation turns out to be better than that of a VHDL reference design. In the following, the main parts of the LAR coder will be presented; we will introduce the basic notions of the CAL language and its infrastructure (edition, simulation and HDL synthesis tools) and the results will be discussed

System level synthesis of dataflow programs: HEVC decoder case study

International audienceWhile dealing with increasing complexity of signal processing algorithms, the primary motivation for the development of High-Level Synthesis (HLS) tools for the automatic generation of Register Transfer Level (RTL) description from high-level description language is the reduction of time-to-market. However, most existing HLS tools operate at the component level, thus the entire system is not taken into consideration. We provide an original technique that raises the level of abstraction to the system level in order to obtain RTL description from a dataflow description. First, we design image processing algorithms using an actor oriented language under the Reconfigurable Video Coding (RVC) standard. Once the design is achieved, we use a dataflow compilation infrastructure called Open RVC-CAL Compiler (Orcc) to generate a C-based code. Afterward, a Xilinx HLS tool called Vivado is used for an automatic generation of synthesizable hardware implementation. In this paper, we show that a simulated hardware code generation of High Efficiency Video Coding (HEVC) under the RVC specifications is rapidly obtained with promising preliminary results

Fast Hardware implementation of an Hadamard Transform Using RVC-CAL Dataflow Programming

International audienceImplementing an algorithm to hardware platforms is generally not an easy task. The algorithm, typically described in a high-level specification language, must be translated to a low-level HDL language. The difference between models of computation (sequential versus fine-grained parallel) limits the efficiency of automatic translation. On the other hand, manual implementation is time-consuming, because the designer must take care of low level details, and write test benches to test the implementation's behavior. This paper presents a global design method going from high level description to implementation. The first step consists in describing an algorithm as a dataflow program with the RVC-CAL language. Next step is the functional verification of this description using a software framework. The final step consists in an automatic generation of an efficient hardware implementation from the dataflow program. The objective was to spend the most part of the conception time in an open source software platform. We used this method to quickly prototype and generate hardware implementation of the Hadamard transform, an algorithm used in many signal processing algorithms, from an RVC-CAL description

Orcc: multimedia development made easy

International audienceIn this paper, we present Orcc, an open-source development environment that aims at enhancing multimedia development by offering all the advantages of dataflow programming: flexibility, portability and scalability. To do so, Orcc embeds two rich eclipse-based editors that provide an easy writing of dataflow applications, a simulator that allows quick validation of the written code, and a multi-target compiler that is able to translate any dataflow program, written in the RVC-CAL language, into an equivalent description in both hardware and software languages. Orcc has already been used to successfully write tens of multimedia applications, such as a video decoder supporting the new High Efficiency Video Coding standard, that clearly demonstrates the ability of the environment to develop complex applications. Moreover, results show scalable performances on multi-core platforms and achieve real-time decoding frame-rate on HD sequences

Synthèse Matérielle Haut Niveau des Programmes Flot de Donnée RVC

The evolution of video processing algorithms involved the advent of several standards. These standards present many common algorithms but designers are not able to reuse them because of their monolithic description. To solve this problem, ISO/IEC MPEG committee created the Reconfigurable Video Coding (RVC) standard based on the idea that processing algorithms can be defined as a library of components defined following the Dataflow Model of Computation and that can be updated separately. Thus, these components of the modular library are standardized instead of the whole decoder. A Dataflow program can be defined as a directed graph where the vertices represent the processes (actors) to be executed and the edges represent the FIFOs used for the communication. The exchanged data is called tokens. This concept insured that the processes are completely independent and only the presence of tokens which allows the firing of a process. To translate this Model of Computation into a functional description, the Cal actor Language (CAL) is considered in this thesis work. This language is standardized by the MPEG-RVC standard. This standard is supported with a complete infrastructure to design and compile the RVC-CAL into hardware and software implementations. The drawback is that the existing hardware compilers present several limitations especially for the validation and the compilation of high level features of the language. For the validation, we propose a functional methodology that allows the validation of the algorithms in all the conception steps. We show in this thesis the important impact of this methodology to reduce the conception time. Concerning the hardware compilation limitations, we introduce an automatic transformation integrated in the code of an RVC-CAL compiler called Orcc (Open RVC-CAL Compiler). This transformation detects the non compliant features and applies the required transformations in the intermediates representation of Orcc to obtain a synthesizable code while keeping the same global behavior of the actor. This transformation solved the main issue of the hardware generation from Dataflow programs. To validate and assess these methodologies, we applied them on the MPEG-4 Part 2 Simple Profile decoder and the LAR still image codec. We present comparison studies for these application contexts.L'évolution des algorithmes de traitement de la vidéo a impliqué l'apparition de plusieurs standards. Ces standards présentent plusieurs algorithmes communs. Cependant, il n'est pas facile de réutiliser ces algorithmes à cause du monolithisme des codes. Pour résoudre ces problèmes, la communauté ISO/IEC MPEG a créé le standard " Reconfigurable Video Coding " (RVC) basé sur le principe que les algorithmes peuvent être définis sous la forme d'une librairie de composants séparés suivant le modèle de calcul flot de données. Ainsi, les composants sont normalisés au lieu du décodeur entier. Un programme flot de données peut être décrit comme un graphe orienté dont les sommets représentent les process (acteurs) à exécuter et les arcs représentent les FIFOs de communication entre ces processes. Les informations échangées dans les FIFOs s'appellent des jetons. Ce concept fait en sorte que les process sont totalement indépendants les uns des autres et c'est seulement la présence de jetons dans les FIFOs qui est responsable du déclanchement d'un process. Pour traduire ce modèle de calcul en une description fonctionnelle, un langage spécifique appelé CAL Actor Language (CAL) est considéré dans ce travail. Ce langage est standardisé par la norme MPEG-RVC sous le nom RVC-CAL. Le standard RVC est supporté par une infrastructure complète pour concevoir et compiler le RVC-CAL en implémentations matérielles et logicielles mais les compilateurs hardware existants présentent plusieurs limitations essentiellement pour la validation et la compilation de certaines structures haut niveau du langage RVC-CAL. Pour la validation, nous proposons une méthodologie fonctionnelle qui permet la validation des algorithmes dans toutes les étapes du flow de conception. Nous montrons dans ce document l'impact important de cette méthodologie sur la réduction du temps de conception. Concernant les limitations de la compilation hardware, nous introduisons une transformation automatique que nous avons intégrée dans le cœur d'un compilateur du langage RVC-CAL appelé Orcc (Open RVC-CAL Compiler). Cette transformation détecte les structures non supportées par les compilateurs hardware et réalise les changements nécessaires dans la représentation intermédiaire de Orcc pour obtenir un code synthétisable tout en conservant le comportement global de l'acteur. Cette transformation a résolu le plus important goulot d'étranglement de la génération hardware à partir des programmes flow de données. Pour évaluer nos méthodologies, nous avons appliqué la vérification fonctionnelle sur plusieurs applications de traitement d'image et de vidéo et nous avons appliqué la génération matérielle automatique sur le décodeur MPEG-4 part 2 Simple Profile et le codec d'images fixes LAR et nous proposons des études comparatives pour ces deux contextes applicatifs

Synthese matérielle haut niveau des programmes flot de données

L EVOLUTION DES ALGORITHMES DE TRAITEMENT DE LA VIDEO A IMPLIQUE L APPARITION DE PLUSIEURS STANDARDS. CES STANDARDS PRESENTENT PLUSIEURS ALGORITHMES COMMUNS. CEPENDANT, IL N EST PAS FACILE DE REUTILISER CES ALGORITHMES A CAUSE DU MONOLITHISME DES CODES. POUR RESOUDRE CES PROBLEMES, LA COMMUNAUTE ISO/IEC MPEG A CREE LE STANDARD RECONFIGURABLE VIDEO CODING (RVC) BASE SUR LE PRINCIPE QUE LES ALGORITHMES PEUVENT ETRE DEFINIS SOUS LA FORME D UNE LIBRAIRIE DE COMPOSANTS SEPARES. AINSI, LES COMPOSANTS SONT NORMALISES AU LIEU DU DECODEUR ENTIER. MPEG-RVC PROPOSE UNE SPECIFICATION HAUT-NIVEAU UNIFIEE DES TECHNOLOGIES MPEG UTILISANT UN LANGAGE ORIENTE FLOT DE DONNEES APPELE CAL (CAL ACTOR LANGUAGE) ET UNE PLATEFORME DE COMPILATION SUR DES CIBLES LOGICIELLES ET MATERIELLES. LE PROBLEME EST QUE LES COMPILATEURS HARDWARE NE SONT PAS CAPABLES DE COMPILER LES STRUCTURES HAUT-NIVEAU DU CAL QUI SONT OMNIPRESENTS DANS LA MAJORITE DES DESIGNS RVC-CAL EVOLUES. DANS CETTE THESE, LE LANGAGE CAL EST UTILISE POUR LE DEVELOPPEMENT DU CODEC D IMAGE FIXE LAR. LE PROBLEME DE LA GENERATION MATERIELLE A ENSUITE ETE RESOLU EN UTILISANT DES TRANSFORMATIONS AUTOMATIQUES DES STRUCTURES HAUT-NIVEAU VERS LEUR EQUIVALENT EN BAS-NIVEAU. CES TRANSFORMATION ONT ETE TESTEES ET VALIDEES SUR DIFFERENTS DESIGNS RVC-CAL.THE EVOLUTION OF VIDEO PROCESSING ALGORITHMS INVOLVED THE ADVENT OF SEVERAL STANDARDS. THESE STANDARDS PRESENT MANY COMMON ALGORITHMS BUT DESIGNERS ARE NOT ABLE TO REUSE THEM BECAUSE OF THEIR MONOLITHIC DESCRIPTION. TO SOLVE THIS PROBLEM, ISO/IEC MPEG COMMITTEE CREATED THE RECONFIGURABLE VIDEO CODING (RVC) STANDARD BASED ON THE IDEA THAT PROCESSING ALGORITHMS CAN BE DEFINED AS A LIBRARY OF COMPONENTS THAT CAN BE UPDATED SEPARATELY. THUS, THESE COMPONENTS OF THE MODULAR LIBRARY ARE STANDARDIZED INSTEAD OF THE WHOLE DECODER. MPEG RVC FRAMEWORK AIMS AT PROVIDING A UNIFIED HIGH-LEVEL SPECIFICATION OF CURRENT MPEG CODING TECHNOLOGIES USING A DATAFLOW LANGUAGE CALLED CAL ACTOR LANGUAGE (CAL). RVC PRESENTS ALSO A COMPILATION FRAMEWORK OF THE CAL FOR HARDWARE AND SOFTWARE TARGETS, BUT HARDWARE COMPILERS CANNOT COMPILE HIGH-LEVEL FEATURES WHICH ARE OMNIPRESENT IN MOST ADVANCED DESIGNS. IN THIS THESIS, THE CAL LANGUAGE IS USED TO DEVELOP A BASELINE OF THE LAR STILL IMAGE CODER. THE PROBLEM OF HARDWARE GENERATION IS LATER RESOLVED USING AUTOMATIC TRANSFORMATIONS OF THE HIGH-LEVEL FEATURES INTO THEIR EQUIVALENT LOW-LEVEL ONES. THESE TRANSFORMATIONS ARE VALIDATED USING DIFFERENT DESIGNS.RENNES-INSA (352382210) / SudocSudocFranceF

Only a level set of a control Lyapunov function for homogeneous systems

summary:In this paper, we generalize Artstein’s theorem and we derive sufficient conditions for stabilization of single-input homogeneous systems by means of an homogeneous feedback law and we treat an application for a bilinear system

Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at providing a unified high-level specification of current MPEG coding technologies using a dataflow language called Cal Actor Language (CAL). CAL is associated with a set of tools to design dataflow applications and to generate hardware and software implementations. Before this work, the existing CAL hardware compilers did not support high-level features of the CAL. After presenting the main notions of the RVC standard, this paper introduces an automatic transformation process that analyses the non-compliant features and makes the required changes in the intermediate representation of the compiler while keeping the same behavior. Finally, the implementation results of the transformation on video and still image decoders are summarized. We show that the obtained results can largely satisfy the real time constraints for an embedded design on FPGA as we obtain a throughput of 73 FPS for MPEG 4 decoder and 34 FPS for coding and decoding process of the LAR coder using a video of CIF image size. This work resolves the main limitation of hardware generation from CAL designs

Efficient System-Level Hardware Synthesis of Dataflow Programs Using Shared Memory Based FIFO HEVC Decoder Case Study

International audienceThe purpose of this paper is to raise the level of abstraction in the design of embedded systems to the system-level. A novel design flow was proposed that enables an efficient hardware implementation of video processing applications described using a Domain-Specific Language (DSL) for dataflow programming. Despite the huge advancements in High-Level Synthesis (HLS) for Field-Programmable Gate Arrays (FPGAs), designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. Moreover, the main downside of the High-Level Synthesis (HLS) tools is the lack of the entire system consideration. As a remedy, in this work, we propose a design flow that combines a dataflow compiler for generating C-based High-Level Synthesis (HLS) descriptions from a dataflow description and a C-to-gate synthesizer for generating Register Transfer Level (RTL) descriptions. The challenge of implementing the communication channels of dataflow programs relying on Model of Computations (MoC) in Field-Programmable Gate Array (FPGA) is the minimization of the communication overhead. In this issue, we introduced a new interface synthesis approach that maps the large amounts of data that multimedia and image processing applications process, to shared memories on the Field-Programmable Gate Array (FPGA). This leads to a tremendous decrease in the latency and an increase in the throughput. These results were demonstrated upon the hardware synthesis of the emerging High-Efficiency Video Coding (HEVC) standard. Simulation results showed that the proposed implementation has increased throughput by a 5.2x speedup and reduced latency by a 3.8x speedup compared to a state-of-the-art implementation