Installation and Commissioning of the CMS Timing, Trigger and Control Distribution System

The Timing, Trigger and Control (TTC) distribution system must ensure high-quality clocking of the CMS experiment to allow the physics potential of the LHC machine to be fully exploited. This key system provides the synchronization tools – bunch clock, first level Triggers and fast commands – that enable all sub-detector systems to take data for the same LHC collision. Its installation is described, along with the tools used to commission and synchronize the system

An electroabsorption modulator-based network architecture for particle physics applications

The forthcoming increase in rate of data production and radiation levels, associated with the transition to High-Luminosity Large Hadron Collider, necessitates a readout link upgrade. Such upgrade is also an opportunity to move to a more efficient network infrastructure through the introduction of new technologies and it is in light of this that we explore the possibility of using a unified optical network architecture based on using Reflective Electroabsorption Modulators at the detector side. We evaluate the performance of the new architecture and investigate the way operating and environmental parameters such as wavelength and temperature affect it

The Versatile Transceiver Proof of Concept

SLHC experiment upgrades will make substantial use of optical links to enable high-speed data readout and control. The Versatile Link project will develop and assess optical link architectures and components suitable for deployment at SLHC. The on-detector element will be bidirectional optoelectronic module: the Versatile Transceiver that will be based on a commercially available module type minimally customized to meet the constraints of the SLHC on-detector environment in terms of mass, volume, power consumption, operational temperature and radiation environment. We report on the first proof of concept phase of the development, showing the steps towards customization and first results of the radiation resistance of candidate optoelectronic components

Passive Optical Networks for the Distribution of Timed Signals in Particle Physics Experiments

A passive optical network for timing distribution applications based on FPGAs has been successfully demonstrated. Deterministic latency was achieved in the critical downstream direction where triggers are distributed while a burst mode receiver was successfully implemented in the upstream direction. Finally, a simple and efficient protocol was introduced for the communication between the OLT and the ONUs in the network that maximizes bandwidth utilization

A Fully Bidirectional Optical Network With Latency Monitoring Capability for the Distribution of Timing-Trigger and Control Signals in High-Energy Physics Experiments

The present paper discusses recent advances on a Passive Optical Network inspired Timing-Trigger and Control scheme for the future upgrade of the TTC system installed in the LHC experiments' and more specifically the currently known as TTCex to TTCrx link. The timing PON is implemented with commercially available FPGAs and 1-Gigabit Ethernet PON transceivers and provides a fixed latency gigabit downlink that can carry level-1 trigger accept decisions and commands as well as an upstream link for feedback from the front-end electronics

A 5 Gb/s Radiation Tolerant Laser Driver

A laser driver for data transmission at 5 Gb/s has been developed as a part of the Giga Bit Transceiver (GBT) project. The Giga Bit Laser Driver (GBLD) targets High Energy Physics (HEP) applications for which radiation tolerance is mandatory. The GBLD ASIC can drive both VCSELs and some types of edge emitting lasers. It is essentially composed of two drivers capable of sinking up to 12 mA each from the load at a maximum data rate of 5 Gb/s, and of a current sink for the laser bias current. The laser driver include also pre-emphasis and duty cycle control capabilities

FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links

The next generation of optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Rate (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in a Xilinx Virtex-5 FPGA device and discusses the experimental results

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS