THE ROLE OF OLED DEVICES IN THE DEVELOPMENT OF SMART CITIES

In the course of the last few years, interest in the development of smart cities and progress of smart buildings has increased significantly. This development has been significantly increased due to the development of new technologies, innovative functional materials, electronic components and other products. At the same time, it is imperative to use those products that contribute to the preservation of the environment, and above all to energy saving. Thus, new technologies are becoming increasingly attractive, such as the one based on OLED (Organic Light Emitting Diode) technology, which is used in the production of mobile phones, tablet computers, other devices, as well as light sources. Although this technology has been generally known for more than half a century, commercial application of OLED components was not possible due to insufficient efficiency of products based on it. However, the continuous improvement of characteristics and efficiency enabled their more significant application in the past few years. The aim of this work is to provide adequate information about the possibilities of applying some innovative technologies in the planning and development of smart cities. Especially, becoming more familiar with the basic properties and application possibilities of OLED devices can lead to the life quality improvements of city spaces users

The comparison of gamma-radiation and electrical stress influences on oxide and interface defects in power VDMOSFET

The behaviour of oxide and interface defects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors, firstly degraded by the gamma-irradiation and electric field and subsequently recovered and annealed, is presented. By analyzing the transfer characteristic shifts, the changes of threshold voltage and underlying changes of gate oxide and interface trap densities during the stress (recovery, annealing) of investigated devices, it is shown that these two types of stress influence differently on the gate oxide and the SiO2-Si interface. [Projekat Ministarstva nauke Republike Srbije, br. OI171026

EFFECTS OF PULSED NEGATIVE BIAS TEMPERATURE STRESSING IN P-CHANNEL POWER VDMOSFETS

Our recent research of the effects of pulsed bias NBT stressing in p-channel power VDMOSFETs is reviewed in this paper. The reduced degradation normally observed under the pulsed stress bias conditions is discussed in terms of the dynamic recovery effects, which are further assesed by varying the duty cycle ratio and frequency of the pulsed stress voltage. The results are analysed in terms of the effects on device lifetime as well. A tendency of stress induced degradation to decrease with lowering the duty cycle and/or increasing the frequency of the pulsed stress voltage, which leads to the increase in device lifetime, is explained in terms of enhanced dynamic recovery effects

Response of Commercial P-Channel Power VDMOS Transistors to Ionizing Irradiation and Bias Temperature Stress

n this paper, the e®ects of successively applied static/pulsed negative bias temperature (NBT)stress and irradiation on commercial p-channel power vertical double-di®used metal-oxidesemiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of thesestresses on the power devices, the relative contributions of gate oxide charge (Not) and interfacetraps (Nit) to threshold voltage shifts are shown and studied. It was shown that when irradi-ation without gate voltage is used, the duration of the pre-irradiation static NBT stress has aslightly larger e®ect on the radiation response of power VDMOS transistors. Regarding the factthat the investigated components are more likely to function in the dynamic mode than thestatic mode in practice, additional analysis was focused on the results obtained during thepulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stressafter the irradiation, the e®ects ofNotneutralization andNitpassivation (usually related toannealing) are more enhanced than the components subjected to the static NBT stress, becauseonly a high temperature is applied during the pulse-o® state. It was observed that in devicespreviously irradiated with gate voltage applied, the decrease of threshold voltage shift is sig-ni ̄cantly greater during the pulsed NBT stress than during the static NBT stres

NBT STRESS AND RADIATION RELATED DEGRADATION AND UNDERLYING MECHANISMS IN POWER VDMOSFETS

In this paper we provide an overview of instabilities observed in commercial power VDMOSFETs subjected to irradiation, NBT stress, and to consecutive exposure to them. The results have indicated that irradiation of previously NBT stressed devices leads to additional threshold voltage shift, while NBT stress effects in previously irradiated devices depend on the gate bias applied during irradiation and on the total dose received. This points to the importance of the order of applied stresses, indicating that for proper insight into the prediction of device behaviour not only harsh conditions, but also the order of exposure have to be considered. It has also been shown that changes in the densities of oxide trapped charge and interface traps during spontaneous recovery after each of applied stresses can be significant, thus leading to additional instability, even though the threshold voltage seems to remain stable, pointing to the need for clarifying the responsible mechanisms

Effects of gate bias stressing in power vdmosfets

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analyzed in terms of the mechanisms responsible. In the case of positive bias stressing, electron tunneling from neutral oxide traps associated with trivalent silicon ≡Sio defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunneling from the charged oxide traps ≡Sio+ to interface-trap precursors ≡Sis-H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunneling from the silicon valence band to oxygen vacancy defects ≡Sio / Sio≡ is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors ≡Sis−Η with the charged oxide traps ≡Sio+ Sio≡ and H+ ions are proposed to be responsible for interface trap buildup

Annealing of radiation-induced defects in burn-in stressed power VDMOSFETs

The annealing of radiation-induced defects in burn-in stressed n-channel power VDMOSFETs with thick gate oxides (100 and 120 nm) is analysed. In comparison with the previous spontaneous recovery, the changes of device electrical parameters observed during annealing are highlighted by the elevated temperature and voltage applied to the gate, and are more pronounced in devices with a 120 nm thick gate oxide. The threshold voltage of VDMOSFETs with a 100 nm thick gate oxide during annealing has an initially slow growth, but then increases rapidly and reaches the value higher than the pre-irradiation one (rebound effect). In the case of devices with a 120 nm thick gate oxide, the threshold voltage behaviour also consists of a slight initial increase followed by a rapid, but dilatory increase, with an obvious tendency to achieve the rebound. The changes of channel carrier mobility during annealing are similar in all samples: at first, it slowly and then rapidly declines, and after reaching the minimum it begins to increase. In the case of VDMOSFETs with a thicker gate oxide, these changes are much slower. The underlying changes in the densities of gate oxide-trapped charge and interface traps are also delayed in devices with a thicker gate oxide. All these phenomena occur with certain delay in burn-in stressed devices compared to unstressed ones. The leading role in the mechanisms responsible for the observed phenomena is attributed to hydrogen related species

Effects of Bias Temperature Stress and Irradiation in Commercial p-Channel Power VDMOS Transistors

The effects of bias temperature stress and irradiation in commercial p-channel power VDMOS transistors were investigated. In order to additionally elucidate the effects that take place in these power devices during the irradiation after the NBT stress, the relative contributions of gate oxide charge (ΔVot/ΔVTH) and interface traps (ΔVit/ΔVTH) to the threshold voltage shifts are presented and analyzed. It was found that in the case of irradiation without gate voltage the duration of the preirradiation NBT stress had a more pronounced impact on the radiation response of power VDMOS transistors, and that the contribution of the oxide trapped charge plays a more pronounced role in components previously NBT stressed for 1 hour than in those stressed for 1 week.MIEL : 32nd International Conference on Microelectronics; September 12-14, 2021, Niš, SerbiaIEEE Catalog No. CFP21432-US